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authorAaron Durbin <adurbin@chromium.org>2016-12-03 22:08:20 -0600
committerAaron Durbin <adurbin@chromium.org>2016-12-15 07:51:35 +0100
commit31be2c969eed74510c3546bad0dbb9a7334f5843 (patch)
treea7b5d682bfe421a34454d320ec78d04e6911f71b /src/soc/intel/common/nvm.c
parentf1f322b1a883e3d50a1907e29b5aa333a0f795a8 (diff)
downloadcoreboot-31be2c969eed74510c3546bad0dbb9a7334f5843.tar.xz
soc/intel/common: remove mrc cache assumptions
Update the mrc cache implementation to use region_file. Instead of relying on memory-mapped access and pointer arithmetic use the region_devices and region_file to obtain the latest data associated with the region. This removes the need for the nvm wrapper as the region_devices can be used directly. Thus, the library is more generic and can be extended to work on different boot mediums. BUG=chrome-os-partner:56151 Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17717 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/common/nvm.c')
-rw-r--r--src/soc/intel/common/nvm.c122
1 files changed, 26 insertions, 96 deletions
diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c
index 99a1fbfb15..b7e0f4e7ac 100644
--- a/src/soc/intel/common/nvm.c
+++ b/src/soc/intel/common/nvm.c
@@ -24,113 +24,43 @@
#include "nvm.h"
#include "spi_flash.h"
-/* This module assumes the flash is memory mapped just below 4GiB in the
- * address space for reading. Also this module assumes an area it erased
- * when all bytes read as all 0xff's. */
-
-static struct spi_flash *flash;
-
-static int nvm_init(void)
+/* Read flash status register to determine if write protect is active */
+int nvm_is_write_protected(void)
{
- if (flash != NULL)
- return 0;
+ u8 sr1;
+ u8 wp_gpio;
+ u8 wp_spi;
- spi_init();
- flash = spi_flash_probe(0, 0);
- if (!flash) {
- printk(BIOS_DEBUG, "Could not find SPI device\n");
- return -1;
- }
-
- return 0;
-}
+ if (!IS_ENABLED(CONFIG_CHROMEOS))
+ return 0;
-/*
- * Convert memory mapped pointer to flash offset.
- *
- * This is weak because not every platforms memory-maps the NVM media in the
- * same manner. This is a stop-gap solution.
- *
- * The root of the problem is that users of this API work in memory space for
- * both reads and writes, but erase and write must be done in flash space. This
- * also only works when the media is memory-mapped, which is no longer
- * universally true. The long-term approach should be to rewrite this and its
- * users to work in flash space, while using rdev_read() instead of rdev_mmap().
- */
-__attribute__((weak))
-uint32_t nvm_mmio_to_flash_offset(void *p)
-{
- return CONFIG_ROM_SIZE + (uintptr_t)p;
-}
+ if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
+ return 0;
-int nvm_is_erased(const void *start, size_t size)
-{
- const uint8_t *cur = start;
- const uint8_t erased_value = 0xff;
+ /* Read Write Protect GPIO if available */
+ wp_gpio = get_write_protect_state();
- while (size > 0) {
- if (*cur != erased_value)
- return 0;
- cur++;
- size--;
+ /* Read Status Register 1 */
+ if (spi_flash_status(boot_device_spi_flash(), &sr1) < 0) {
+ printk(BIOS_ERR, "Failed to read SPI status register 1\n");
+ return -1;
}
- return 1;
-}
+ wp_spi = !!(sr1 & 0x80);
-int nvm_erase(void *start, size_t size)
-{
- if (nvm_init() < 0)
- return -1;
- return spi_flash_erase(flash, nvm_mmio_to_flash_offset(start), size);
-}
+ printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n",
+ wp_gpio, wp_spi);
-/* Write data to NVM. Returns 0 on success < 0 on error. */
-int nvm_write(void *start, const void *data, size_t size)
-{
- if (nvm_init() < 0)
- return -1;
- return spi_flash_write(flash, nvm_mmio_to_flash_offset(start), size,
- data);
+ return wp_gpio && wp_spi;
}
-/* Read flash status register to determine if write protect is active */
-int nvm_is_write_protected(void)
+/* Apply protection to a range of flash */
+int nvm_protect(const struct region *r)
{
- if (nvm_init() < 0)
- return -1;
-
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
- u8 sr1;
- u8 wp_gpio;
- u8 wp_spi;
-
- /* Read Write Protect GPIO if available */
- wp_gpio = get_write_protect_state();
-
- /* Read Status Register 1 */
- if (spi_flash_status(flash, &sr1) < 0) {
- printk(BIOS_ERR,
- "Failed to read SPI status register 1\n");
- return -1;
- }
- wp_spi = !!(sr1 & 0x80);
-
- printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n",
- wp_gpio, wp_spi);
+ if (!IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT))
+ return 0;
- return wp_gpio && wp_spi;
- }
- return 0;
-}
+ if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
+ return 0;
-/* Apply protection to a range of flash */
-int nvm_protect(void *start, size_t size)
-{
-#if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT)
- if (nvm_init() < 0)
- return -1;
- return spi_flash_protect(nvm_mmio_to_flash_offset(start), size);
-#else
- return -1;
-#endif
+ return spi_flash_protect(region_offset(r), region_sz(r));
}