baytrail: Move MRC cache code to a common directory

This common code can be shared across Intel SOCs.

Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/196263
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6967
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

1 files changed, 82 insertions, 0 deletions

diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c
new file mode 100644
index 0000000000..791422fe30
--- /dev/null
+++ b/src/soc/intel/common/nvm.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <console/console.h>
+#include <string.h>
+#include <spi-generic.h>
+#include <spi_flash.h>
+#include "nvm.h"
+
+/* This module assumes the flash is memory mapped just below 4GiB in the
+ * address space for reading. Also this module assumes an area it erased
+ * when all bytes read as all 0xff's. */
+
+static struct spi_flash *flash;
+
+static int nvm_init(void)
+{
+	if (flash != NULL)
+		return 0;
+
+	spi_init();
+	flash = spi_flash_probe(0, 0);
+	if (!flash) {
+		printk(BIOS_DEBUG, "Could not find SPI device\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+/* Convert memory mapped pointer to flash offset. */
+static inline uint32_t to_flash_offset(void *p)
+{
+	return CONFIG_ROM_SIZE + (uintptr_t)p;
+}
+
+int nvm_is_erased(const void *start, size_t size)
+{
+	const uint8_t *cur = start;
+	const uint8_t erased_value = 0xff;
+
+	while (size > 0) {
+		if (*cur != erased_value)
+			return 0;
+		cur++;
+		size--;
+	}
+	return 1;
+}
+
+int nvm_erase(void *start, size_t size)
+{
+	if (nvm_init() < 0)
+		return -1;
+	return flash->erase(flash, to_flash_offset(start), size);
+}
+
+/* Write data to NVM. Returns 0 on success < 0 on error.  */
+int nvm_write(void *start, const void *data, size_t size)
+{
+	if (nvm_init() < 0)
+		return -1;
+	return flash->write(flash, to_flash_offset(start), size, data);
+}