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author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-04-20 15:24:54 -0700 |
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committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-06-24 17:05:06 +0200 |
commit | 0946ec37aa4660ecf16d66cb1174a68df0afc4f0 (patch) | |
tree | 7be11b3d97f09f9f5fd176b275d0df3a9c2692e4 /src/soc/intel/common/ramstage.h | |
parent | 4a8c19cc90464ad215395bd116c9dc95fc682cac (diff) | |
download | coreboot-0946ec37aa4660ecf16d66cb1174a68df0afc4f0.tar.xz |
Intel Common SOC: Add romstage support
Provide a common romstage implementation for the Intel SOCs.
BRANCH=none
BUG=None
TEST=Build for Braswell
Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10050
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/ramstage.h')
-rw-r--r-- | src/soc/intel/common/ramstage.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/soc/intel/common/ramstage.h b/src/soc/intel/common/ramstage.h new file mode 100644 index 0000000000..414142a8ae --- /dev/null +++ b/src/soc/intel/common/ramstage.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _INTEL_COMMON_RAMSTAGE_H_ +#define _INTEL_COMMON_RAMSTAGE_H_ + +#include <fsp_util.h> +#include <soc/intel/common/util.h> +#include <stdint.h> + +/* Perform Intel silicon init. */ +void intel_silicon_init(void); +/* Called after the silicon init code has run. */ +void soc_after_silicon_init(void); +/* Initialize UPD data before SiliconInit call. */ +void soc_silicon_init_params(SILICON_INIT_UPD *params); +void mainboard_silicon_init_params(SILICON_INIT_UPD *params); +void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, + SILICON_INIT_UPD *new); +void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params); + +#endif /* _INTEL_COMMON_RAMSTAGE_H_ */ |