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author | Aaron Durbin <adurbin@chromium.org> | 2015-09-16 15:18:04 -0500 |
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committer | Aaron Durbin <adurbin@gmail.com> | 2015-10-11 23:54:53 +0000 |
commit | e1ecfc93af4918c2a9a4647cf550cb7ecc2b92d6 (patch) | |
tree | f86a6b4fdec14666a4e0fca1618441f52ea526ad /src/soc/intel/common/romstage.c | |
parent | 8ef9c5660211719f974da1c452257a94c167bfed (diff) | |
download | coreboot-e1ecfc93af4918c2a9a4647cf550cb7ecc2b92d6.tar.xz |
intel: update common and FSP cache-as-ram parameters
Instead of just passing bits, tsc_low, tsc_high, and an
opaque pointer to chipset context those fields are bundled
into a cache_as_ram_params struct. Additionally, a new
struct fsp_car_context is created to hold the FSP
information. These could be combined as the existing
romstage code assumes what the chipset_context values are, but
I'm leaving the concept of "common" alone for the time being.
While working in that area the ABI between assembly and C code
has changed to just pass a single pointer to cache_as_ram_params
struct. Lastly, validate the bootloader cache-as-ram region
with the Kconfig options.
BUG=chrome-os-partner:44676
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: Ib2a0e38477ef7c15cff1836836cfb55e5dc8a58e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/300190
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Change-Id: Ic5a0daa4e2fe5eda0c4d2a45d86baf14ff7b2c6c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11809
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/common/romstage.c')
-rw-r--r-- | src/soc/intel/common/romstage.c | 30 |
1 files changed, 20 insertions, 10 deletions
diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c index 0d5e85fa67..f4ee250203 100644 --- a/src/soc/intel/common/romstage.c +++ b/src/soc/intel/common/romstage.c @@ -32,6 +32,7 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <elog.h> +#include <fsp/util.h> #include <memory_info.h> #include <reset.h> #include <romstage_handoff.h> @@ -48,22 +49,22 @@ #include <vendorcode/google/chromeos/chromeos.h> /* Entry from cache-as-ram.inc. */ -asmlinkage void *romstage_main(unsigned int bist, - uint32_t tsc_low, uint32_t tsc_high, - void *chipset_context) +asmlinkage void *romstage_main(struct cache_as_ram_params *car_params) { void *top_of_stack; struct pei_data pei_data; + struct fsp_car_context *fsp_car_context; struct romstage_params params = { - .bist = bist, + .bist = car_params->bist, .pei_data = &pei_data, - .chipset_context = chipset_context, + .chipset_context = car_params->chipset_context, }; + fsp_car_context = car_params->chipset_context; post_code(0x30); /* Save timestamp data */ - timestamp_init((((uint64_t)tsc_high) << 32) | (uint64_t)tsc_low); + timestamp_init(car_params->tsc); timestamp_add_now(TS_START_ROMSTAGE); memset(&pei_data, 0, sizeof(pei_data)); @@ -76,9 +77,8 @@ asmlinkage void *romstage_main(unsigned int bist, console_init(); /* Display parameters */ - printk(BIOS_SPEW, "bist: 0x%08x\n", bist); - printk(BIOS_SPEW, "tsc_low: 0x%08x\n", tsc_low); - printk(BIOS_SPEW, "tsc_hi: 0x%08x\n", tsc_high); + printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist); + printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc); printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", CONFIG_MMCONF_BASE_ADDRESS); printk(BIOS_INFO, "Using: %s\n", @@ -88,7 +88,17 @@ asmlinkage void *romstage_main(unsigned int bist, /* Display FSP banner */ printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); - print_fsp_info(params.chipset_context); + print_fsp_info(fsp_car_context->fih); + + if (fsp_car_context->bootloader_car_start != CONFIG_DCACHE_RAM_BASE || + fsp_car_context->bootloader_car_end != + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) { + printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n", + CONFIG_DCACHE_RAM_BASE, + CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE, + (long)fsp_car_context->bootloader_car_start, + (long)fsp_car_context->bootloader_car_end); + } /* Get power state */ params.power_state = fill_power_state(); |