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author | Aaron Durbin <adurbin@chromium.org> | 2015-09-24 12:26:31 -0500 |
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committer | Aaron Durbin <adurbin@gmail.com> | 2015-10-11 23:55:45 +0000 |
commit | e6af4be1587f34f2f79d6e8b9ece94cfa7cd4c8e (patch) | |
tree | 94503e1a9526b30ff2356357d4a91a4e89900034 /src/soc/intel/common/romstage.h | |
parent | cc5ac17fab97bd16f3122bb492fbdc28644c8567 (diff) | |
download | coreboot-e6af4be1587f34f2f79d6e8b9ece94cfa7cd4c8e.tar.xz |
intel fsp1_1: prepare for romstage vboot verification split
In order to introduce a verstage which performs vboot
verification the cache-as-ram environment needs to be
generalized and split into pieces that can be utilized
in romstage and/or verstage. Therefore, the romstage
pieces were removed from the cache-as-ram specific pieces
that are generic:
- Add fsp/car.h to house the declarations for functions in
the cache-as-ram environment
- Only have cache_as_ram_params which are isolated form the
cache-as-ram environment aside from FSP_INFO_HEADER.
- Hardware requirements for console initialization is done
in the cache-as-ram specific files.
- Provide after_raminit.S which can be included from a
romstage separated from cache-as-ram as well as one that
is tightly coupled to the cache-as-ram environment.
- Update the fallout from the API changes in
soc/intel/{braswell,common,skylake}.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302481
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11816
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/common/romstage.h')
-rw-r--r-- | src/soc/intel/common/romstage.h | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h index ac1d6a0d38..272679f8d9 100644 --- a/src/soc/intel/common/romstage.h +++ b/src/soc/intel/common/romstage.h @@ -24,17 +24,12 @@ #include <stdint.h> #include <arch/cpu.h> #include <memory_info.h> +#include <fsp/car.h> #include <fsp/util.h> #include <soc/intel/common/util.h> #include <soc/pei_data.h> #include <soc/pm.h> /* chip_power_state */ -struct cache_as_ram_params { - uint64_t tsc; - uint32_t bist; - void *chipset_context; -}; - struct romstage_params { unsigned long bist; struct chipset_power_state *power_state; @@ -80,7 +75,6 @@ struct romstage_params { void mainboard_check_ec_image(struct romstage_params *params); void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params); -void mainboard_pre_console_init(void); void mainboard_romstage_entry(struct romstage_params *params); void mainboard_save_dimm_info(struct romstage_params *params); void mainboard_add_dimm_info(struct romstage_params *params, @@ -88,18 +82,14 @@ void mainboard_add_dimm_info(struct romstage_params *params, int channel, int dimm, int index); void raminit(struct romstage_params *params); void report_memory_config(void); -asmlinkage void romstage_after_car(void *chipset_context); void romstage_common(struct romstage_params *params); -asmlinkage void *romstage_main(struct cache_as_ram_params *car_params); +asmlinkage void *romstage_main(FSP_INFO_HEADER *fih); void *setup_stack_and_mtrrs(void); void soc_after_ram_init(struct romstage_params *params); -void soc_after_temp_ram_exit(void); void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new); void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd); -void soc_pre_console_init(void); void soc_pre_ram_init(struct romstage_params *params); -void soc_romstage_init(struct romstage_params *params); #endif /* _COMMON_ROMSTAGE_H_ */ |