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authorSubrata Banik <subrata.banik@intel.com>2017-11-09 15:04:09 +0530
committerAaron Durbin <adurbin@chromium.org>2017-11-10 16:37:38 +0000
commit05e06cd0bef0d85de2466cfccf7c8ce375f950ee (patch)
tree6f17ea57c10bf91baa3337cef14c845aaee73ebd /src/soc/intel/common
parent330dc10cfd956df91855593b6f33b502c6883c55 (diff)
downloadcoreboot-05e06cd0bef0d85de2466cfccf7c8ce375f950ee.tar.xz
soc/intel/common: Fix CSE common code to accomodate Skylake/Kabylake
This patch ensures Skylake/Kabylake soc can make use of common CSE code in order to perform global reset using HECI interface. TEST=Build and boot on soraka/eve/reef/cnl-rvp Change-Id: I49b89be8106a19cde1eb9b488ac660637537ad71 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/block/cse/cse.c25
1 files changed, 22 insertions, 3 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 617684c0f0..53c4a81959 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -14,6 +14,7 @@
*/
#include <arch/early_variables.h>
+#include <assert.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <delay.h>
@@ -21,13 +22,11 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <intelblocks/cse.h>
+#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <string.h>
#include <timer.h>
-/* default window for early boot, must be at least 12 bytes in size */
-#define HECI1_BASE_ADDRESS 0xfed1a000
-
/* Wait up to 15 sec for HECI to get ready */
#define HECI_DELAY_READY (15 * 1000)
/* Wait up to 100 usec between circullar buffer polls */
@@ -108,15 +107,35 @@ void heci_init(uintptr_t tempbar)
cse->sec_bar = tempbar;
}
+/* Get HECI BAR 0 from PCI configuration space */
+static uint32_t get_cse_bar(void)
+{
+ uintptr_t bar;
+
+ bar = pci_read_config32(PCH_DEV_CSE, PCI_BASE_ADDRESS_0);
+ assert(bar != 0);
+ /*
+ * Bits 31-12 are the base address as per EDS for SPI,
+ * Don't care about 0-11 bit
+ */
+ return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+}
+
static uint32_t read_bar(uint32_t offset)
{
struct cse_device *cse = car_get_var_ptr(&g_cse);
+ /* Reach PCI config space to get BAR incase CAR global not available */
+ if (!cse->sec_bar)
+ cse->sec_bar = get_cse_bar();
return read32((void *)(cse->sec_bar + offset));
}
static void write_bar(uint32_t offset, uint32_t val)
{
struct cse_device *cse = car_get_var_ptr(&g_cse);
+ /* Reach PCI config space to get BAR incase CAR global not available */
+ if (!cse->sec_bar)
+ cse->sec_bar = get_cse_bar();
return write32((void *)(cse->sec_bar + offset), val);
}