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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2016-07-24 18:12:09 +0200
committerRonald G. Minnich <rminnich@gmail.com>2016-07-28 18:31:28 +0200
commit8e63017096e23a962bc017a6c0503dddc57f63e3 (patch)
tree855d859c03b05b919ab150881f4ec0c001c4aa6a /src/soc/intel/common
parent62bd9f93dd58e32baeddb4404fec6d04c9be3484 (diff)
downloadcoreboot-8e63017096e23a962bc017a6c0503dddc57f63e3.tar.xz
arch/riscv: Refactor bootblock.S
A few things are currently missing: - The trap handler doesn't set the stack pointer, which can easily result in trap loops or memory corruptions. - The SBI trampolin page (as described in version 1.9 of the RISC-V Privileged Architecture Specification), has been removed for now. Change-Id: Id89c859fab354501c94a0e82d349349c29fa4cc6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15591 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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