diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2016-11-21 09:19:53 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-11-22 17:39:07 +0100 |
| commit | d0c00052d32ed2ea461811632197845120ca8a08 (patch) | |
| tree | 03c311038a65edb62bfe6a763a4667a5af408239 /src/soc/intel/common | |
| parent | d2fb6ae813880b8fd1b3983e0e61c7e51fb9b20b (diff) | |
| download | coreboot-d0c00052d32ed2ea461811632197845120ca8a08.tar.xz | |
soc/intel: Use correct terminology for SPI flash operations
FPR is an attribute of the SPI flash component and not of the SPI bus
itself. Rename functions, file names and Kconfig option to make sure
this is conveyed correctly.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Change-Id: I9f06f1a8ee28b8c56db64ddd6a19dd9179c54f50
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17560
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/nvm.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/spi_flash.c (renamed from src/soc/intel/common/spi.c) | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/spi_flash.h (renamed from src/soc/intel/common/spi.h) | 7 |
5 files changed, 11 insertions, 6 deletions
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 5d8bf6664c..7ae7e60396 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -9,7 +9,7 @@ config CACHE_MRC_SETTINGS bool "Save cached MRC settings" default n -config SOC_INTEL_COMMON_SPI_PROTECT +config SOC_INTEL_COMMON_SPI_FLASH_PROTECT bool default n diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 38903a0ae7..d6e1e751d6 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -20,7 +20,7 @@ postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_SPI_PROTECT) += spi.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_SPI_FLASH_PROTECT) += spi_flash.c ramstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += util.c diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index e44fb940b7..99a1fbfb15 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -22,7 +22,7 @@ #include <spi_flash.h> #include <vendorcode/google/chromeos/chromeos.h> #include "nvm.h" -#include "spi.h" +#include "spi_flash.h" /* This module assumes the flash is memory mapped just below 4GiB in the * address space for reading. Also this module assumes an area it erased diff --git a/src/soc/intel/common/spi.c b/src/soc/intel/common/spi_flash.c index e73a55e125..c7717c9fe9 100644 --- a/src/soc/intel/common/spi.c +++ b/src/soc/intel/common/spi_flash.c @@ -15,7 +15,7 @@ #include <arch/io.h> #include <console/console.h> -#include "spi.h" +#include "spi_flash.h" /* * Protect range of SPI flash defined by [start, start+size-1] using Flash @@ -29,7 +29,7 @@ int spi_flash_protect(u32 start, u32 size) int fpr; uintptr_t fpr_base; - if (spi_get_fpr_info(&fpr_info) == -1) { + if (spi_flash_get_fpr_info(&fpr_info) == -1) { printk(BIOS_ERR, "ERROR: FPR Info not found!\n"); return -1; } diff --git a/src/soc/intel/common/spi.h b/src/soc/intel/common/spi_flash.h index a89f7925aa..d6bb079dbb 100644 --- a/src/soc/intel/common/spi.h +++ b/src/soc/intel/common/spi_flash.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef __INTEL_COMMON_SPI_FLASH_H__ +#define __INTEL_COMMON_SPI_FLASH_H__ + #define SPI_FPR_SHIFT 12 #define SPI_FPR_MASK 0x7fff #define SPI_FPR_BASE_SHIFT 0 @@ -36,10 +39,12 @@ struct fpr_info { * * On success return 0 else -1. */ -int spi_get_fpr_info(struct fpr_info *info); +int spi_flash_get_fpr_info(struct fpr_info *info); /* * Protect range of SPI flash defined by [start, start+size-1] using Flash * Protected Range (FPR) register if available. */ int spi_flash_protect(u32 start, u32 size); + +#endif /* __INTEL_COMMON_SPI_FLASH_H__ */ |