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| author | Subrata Banik <subrata.banik@intel.com> | 2018-10-08 11:04:24 +0530 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-10-09 20:11:37 +0000 |
| commit | 50cdce95751d25e73abfe0bdd02c95029db8b7df (patch) | |
| tree | e0196e2442224cee4da4b7e3a0a12a72cbc448fe /src/soc/intel/common | |
| parent | ee941635e668e48d704bbeef519b13b0b66ef38a (diff) | |
| download | coreboot-50cdce95751d25e73abfe0bdd02c95029db8b7df.tar.xz | |
soc/intel/common/acpi: Fix ACPI Namespace lookup failure, AE_ALREADY_EXISTS issue
This patch fixes below ACPI compilation issue:
Found 1 external control methods, reparsing with new information
Pass 1 parse of [DSDT]
ACPI Error: [EPCS] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660)
ACPI Error: [EMNA] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660)
ACPI Error: [ELNG] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660)
Pass 2 parse of [DSDT]
ACPI Warning: NsLookup: Type mismatch on EPCS (Integer), searching for (RegionField) (20160318/nsaccess-664)
ACPI Warning: NsLookup: Type mismatch on EMNA (Integer), searching for (RegionField) (20160318/nsaccess-664)
ACPI Warning: NsLookup: Type mismatch on ELNG (Integer), searching for (RegionField) (20160318/nsaccess-664)
Parsing Deferred Opcodes (Methods/Buffers/Packages/Regions)
TEST=Able to build sgx.asl without any ASL error.
Change-Id: If4e7d4c66b6aab6c081fa272d8c2c9a1f0651ef7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/acpi/sgx.asl | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/src/soc/intel/common/acpi/sgx.asl b/src/soc/intel/common/acpi/sgx.asl index 43de44f33c..593821996c 100644 --- a/src/soc/intel/common/acpi/sgx.asl +++ b/src/soc/intel/common/acpi/sgx.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. + * Copyright (C) 2017-2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,10 +13,6 @@ * GNU General Public License for more details. */ -External(\_SB.EPCS, IntObj) // Enclave Page Cache (EPC) Status -External(\_SB.EMNA, IntObj) // EPC base address -External(\_SB.ELNG, IntObj) // EPC length - Scope(\_SB) { // Secure Enclave memory @@ -54,15 +50,15 @@ Scope(\_SB) CreateQwordField (RBUF, ^BAR0._MIN, EMIN) CreateQwordField (RBUF, ^BAR0._MAX, EMAX) CreateQwordField (RBUF, ^BAR0._LEN, ELEN) - Store (\_SB.EMNA, EMIN) - Store (\_SB.ELNG, ELEN) - Subtract (Add (\_SB.EMNA, \_SB.ELNG), 1, EMAX) + Store (EMNA, EMIN) + Store (ELNG, ELEN) + Subtract (Add (EMNA, ELNG), 1, EMAX) Return (RBUF) } Method (_STA, 0x0, NotSerialized) { - If (LNotEqual (\_SB.EPCS, 0)) + If (LNotEqual (EPCS, 0)) { Return (0xF) } |