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| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2017-08-28 15:30:20 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-15 16:21:29 +0000 |
| commit | 6a051f2b49d5d4b9605f4a4a2dfe46cd770704b3 (patch) | |
| tree | 64f7f513d57c437e7ad7070014f8971eda4ed63b /src/soc/intel/common | |
| parent | 57c5af30ddf82585813bfdcb7336d6babe9cb486 (diff) | |
| download | coreboot-6a051f2b49d5d4b9605f4a4a2dfe46cd770704b3.tar.xz | |
soc/intel/skylake: Move UNCORE PRMRR base and mask defines.
UNCORE PRMRR BASE and MASK MSRs are not common, so move to
SOC specific header file and rename the #define to start with MSR_*
Change-Id: I799c43f0b7a9eec5b3b69ab0f5100935c7f3f170
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 55d0bfd458..6236915c53 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -72,8 +72,6 @@ #define PRMRR_PHYS_MASK_VALID (1 << 11) #define MSR_POWER_CTL 0x1fc #define MSR_EVICT_CTL 0x2e0 -#define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4 -#define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5 #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 #define IA32_MC0_CTL 0x400 |