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| author | Duncan Laurie <dlaurie@chromium.org> | 2016-11-03 10:43:14 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-07 20:40:48 +0100 |
| commit | a87170b166aa20405be629c22fe6d54cc315e8e5 (patch) | |
| tree | 587ddec68577c5fbf36b2681f033c1f330c3850e /src/soc/intel/common | |
| parent | 2f3736e7aceb289d51a54679747d65eb09c1e0f1 (diff) | |
| download | coreboot-a87170b166aa20405be629c22fe6d54cc315e8e5.tar.xz | |
lpss_i2c: Increase transaction timeout
When doing long transcations on an I2C bus at standard speed we saw
that long transactions could go over the 4ms limit while waiting for
it to complete on the bus.
Increase this so we can use standard speed for testing and debug in
firmware. (as there is no way to force standard speed in the kernel)
BUG=chrome-os-partner:58666
TEST=boot eve board with cr50 TPM and I2C bus at 100khz
Change-Id: I2987ae6a5aa024b373eb088767194c70b0918b6f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17213
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/lpss_i2c.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/common/lpss_i2c.c b/src/soc/intel/common/lpss_i2c.c index 01747926d0..58d44b85dd 100644 --- a/src/soc/intel/common/lpss_i2c.c +++ b/src/soc/intel/common/lpss_i2c.c @@ -73,8 +73,8 @@ struct lpss_i2c_regs { uint32_t comp_type; } __attribute__((packed)); -/* Use a ~4ms timeout for various operations */ -#define LPSS_I2C_TIMEOUT_US 4000 +/* Use a ~10ms timeout for various operations */ +#define LPSS_I2C_TIMEOUT_US 10000 /* High and low times in different speed modes (in ns) */ enum { |