diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2019-08-06 13:34:03 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-09 01:23:19 +0000 |
| commit | c6e37081749c3518a87a24b2b92bd9b0e293ebbf (patch) | |
| tree | f166d1f117a464dcb849ac6dd17e9e74443cac89 /src/soc/intel/common | |
| parent | 3a4511eb6cb395b86f425bd6a8474ab35c554531 (diff) | |
| download | coreboot-c6e37081749c3518a87a24b2b92bd9b0e293ebbf.tar.xz | |
soc/intel/common/gspi: Use GSPI bus id to map to the controller
Currently SPI bus id is used to map to the controller in order to set
the controller state. In certain platforms SPI bus id might not be
exactly the same as GSPI bus id. For example, in Intel platforms SPI bus
id 0 maps to fast spi i.e. SPI going to the flash and SPI bus id 1 .. n
map to GSPI bus id 0 .. n-1. Hence using SPI bus id leads to mapping to the
GSPI controller that is not enabled. Use the GSPI id bus so that the right
controller is set to active state. This fixes the regression introduced
by CB:34449
BUG=b:135941367
TEST=Boot to ChromeOS.
Change-Id: I792ab1fa6529f5317218896ad05321f8f17cedcd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/gspi/gspi.c | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index beb12fb231..f937bd6eed 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -452,15 +452,6 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev) struct gspi_ctrlr_params params, *p = ¶ms; const struct device *device; - devfn = gspi_soc_bus_to_devfn(dev->bus); - if (devfn < 0) { - printk(BIOS_ERR, "%s: No GSPI controller found on SPI bus %u.\n", - __func__, dev->bus); - return -1; - } - - device = pcidev_path_on_root(devfn); - /* Only chip select 0 is supported. */ if (dev->cs != 0) { printk(BIOS_ERR, "%s: Invalid CS value: cs=%u.\n", __func__, @@ -478,6 +469,13 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev) return -1; } + devfn = gspi_soc_bus_to_devfn(p->gspi_bus); + /* + * devfn is already validated as part of gspi_ctrlr_params_init. + * No need to revalidate it again. + */ + device = pcidev_path_on_root(devfn); + /* Ensure controller is in D0 state */ lpss_set_power_state(device, STATE_D0); |