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authorLee Leahy <leroy.p.leahy@intel.com>2016-07-30 07:17:13 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2016-08-01 06:16:05 +0200
commit4c18de2de918e96ceeca87d2fb51853c286548ee (patch)
treeb71035c563e423403b7e8676d9b0b065b392ab5b /src/soc/intel/common
parent0c1843aeb9559424c04c89e80a8c540e5634802d (diff)
downloadcoreboot-4c18de2de918e96ceeca87d2fb51853c286548ee.tar.xz
soc/intel/common: Enable MTRR display during bootblock & postcar
Update Makefile.inc to allow MTRR display during bootblock and postcar. TEST=Build and run on Galileo Gen2 Change-Id: If12896df46b9edfc9fff3fab3a12d2dae23517a3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15990 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/Makefile.inc4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 429c61c2e1..13ba21bcbe 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -1,5 +1,7 @@
ifeq ($(CONFIG_SOC_INTEL_COMMON),y)
+bootblock-y += util.c
+
verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c
verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
@@ -12,6 +14,8 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
romstage-y += util.c
romstage-$(CONFIG_MMA) += mma.c
+postcar-y += util.c
+
ramstage-y += hda_verb.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c