summaryrefslogtreecommitdiff
path: root/src/soc/intel/common
diff options
context:
space:
mode:
authorShamile Khan <shamile.khan@intel.com>2018-04-09 16:44:23 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-04-11 09:31:20 +0000
commite9eb14079c22f00342f8f884791e24d82980c2b4 (patch)
treeaad6838527a06637a78268cd3d09f9b00609b68f /src/soc/intel/common
parentbb3a5efaf7d684898899b97532629a32c575ae9c (diff)
downloadcoreboot-e9eb14079c22f00342f8f884791e24d82980c2b4.tar.xz
soc/intel/common/block/gspi: Set Clock Update Bit for clock updates.
This is required for clock parameter settings to take effect. BUG=b:75306520 BRANCH=None TEST=On Octopus, used a scope to check that spi_clk fed to tpm is 1 MHz Change-Id: Icdb617aa4aa944d46b3a56dab88d2008b01dea0d Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/block/gspi/gspi.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index e4e44c22bb..8bf27de1cf 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -465,7 +465,8 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev)
* Program m/n divider.
* Set m and n to 1, so that this divider acts as a pass-through.
*/
- clocks = (1 << CLOCKS_N_SHIFT) | (1 << CLOCKS_M_SHIFT) | CLOCKS_ENABLE;
+ clocks = (1 << CLOCKS_N_SHIFT) | (1 << CLOCKS_M_SHIFT) | CLOCKS_ENABLE |
+ CLOCKS_UPDATE;
gspi_write_mmio_reg(p, CLOCKS, clocks);
udelay(10);