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authorDuncan Laurie <dlaurie@chromium.org>2016-09-12 11:21:40 -0700
committerAaron Durbin <adurbin@chromium.org>2016-09-14 22:24:06 +0200
commitf8a7b2c008f45e91e8bc52fbe2d4e0083dab250b (patch)
treef5d5388981df059f009de6c07c7dbf3fcbff6900 /src/soc/intel/common
parent772555a214e023c6e3dd267d296bef23242f3638 (diff)
downloadcoreboot-f8a7b2c008f45e91e8bc52fbe2d4e0083dab250b.tar.xz
lpss_i2c: Add Kconfig option to enable debug
It is very useful to have the ability to see I2C transactions performed by the host firmware. This patch adds a simple Kconfig option that will enable debug output. Change-Id: I55f1ff273290e2f4fbfaea56091b2df3fc49fe61 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16590 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/Kconfig8
-rw-r--r--src/soc/intel/common/lpss_i2c.c13
2 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 7726bf121f..8eae23b6e7 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -62,6 +62,14 @@ config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
No default is set here as this is an SOC-specific value and must
be provided by the SOC when it selects this driver.
+config SOC_INTEL_COMMON_LPSS_I2C_DEBUG
+ bool "Enable debug output for LPSS I2C transactions"
+ default n
+ depends on SOC_INTEL_COMMON_LPSS_I2C
+ help
+ Enable debug output for I2C transactions. This can be useful
+ when debugging I2C drivers.
+
config MMA
bool "enable MMA (Memory Margin Analysis) support"
default n
diff --git a/src/soc/intel/common/lpss_i2c.c b/src/soc/intel/common/lpss_i2c.c
index 76c3d14d70..01747926d0 100644
--- a/src/soc/intel/common/lpss_i2c.c
+++ b/src/soc/intel/common/lpss_i2c.c
@@ -265,6 +265,11 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
/* Process each segment */
while (count--) {
+ if (CONFIG_SOC_INTEL_COMMON_LPSS_I2C_DEBUG)
+ printk(BIOS_DEBUG, "i2c %u:%02x %s %d bytes : ",
+ bus, segments->chip, segments->read ? "R" : "W",
+ segments->len);
+
/* Set target slave address */
write32(&regs->target_addr, segments->chip);
@@ -283,6 +288,14 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
goto out;
}
}
+
+ if (CONFIG_SOC_INTEL_COMMON_LPSS_I2C_DEBUG) {
+ int j;
+ for (j = 0; j < segments->len; j++)
+ printk(BIOS_DEBUG, "%02x ", segments->buf[j]);
+ printk(BIOS_DEBUG, "\n");
+ }
+
segments++;
}