diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-08-04 15:58:26 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-08-10 16:24:57 +0000 |
| commit | 3406dd64c328bf0f2f1902d42b239f84c136e4f0 (patch) | |
| tree | 3a041bafb43a260432cb0c9e2f769e5b177ad9fe /src/soc/intel/common | |
| parent | 836f94c6126b8a9529321c6af71babdae3202592 (diff) | |
| download | coreboot-3406dd64c328bf0f2f1902d42b239f84c136e4f0.tar.xz | |
soc/intel/common/uart: Refactor uart_common_init
1. Create a new function uart_lpss_init which takes the UART LPSS
controller out of reset and initializes and enables clock.
2. Instead of passing in m/n clock divider values as parameters to
uart_common_init, introduce Kconfig variables so that uart_lpss_init
can use the values directly without having to query the SoC.
BUG=b:64030366
TEST=Verified that UART still works on APL and KBL boards.
Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/uart.h | 8 | ||||
| -rw-r--r-- | src/soc/intel/common/block/uart/Kconfig | 12 | ||||
| -rw-r--r-- | src/soc/intel/common/block/uart/uart.c | 18 |
3 files changed, 30 insertions, 8 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index b46edd76d7..9ec5004e08 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -19,8 +19,12 @@ #include <arch/io.h> #include <device/device.h> -void uart_common_init(device_t dev, uintptr_t baseaddr, - uint32_t clk_m_val, uint32_t clk_n_val); +/* + * Common routine to initialize UART controller PCI config space, take it out of + * reset and configure M/N dividers. + */ +void uart_common_init(device_t dev, uintptr_t baseaddr); + void pch_uart_read_resources(struct device *dev); diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig index 103659f4c4..f4a0e4e4b9 100644 --- a/src/soc/intel/common/block/uart/Kconfig +++ b/src/soc/intel/common/block/uart/Kconfig @@ -3,3 +3,15 @@ config SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_LPSS help Intel Processor common UART support + +config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL + depends on SOC_INTEL_COMMON_BLOCK_UART + hex + help + Clock m-divisor value for m/n divider + +config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL + depends on SOC_INTEL_COMMON_BLOCK_UART + hex + help + Clock m-divisor value for m/n divider diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index e8f1bc8094..be30464b13 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -19,8 +19,17 @@ #include <intelblocks/lpss.h> #include <intelblocks/uart.h> -void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val, - uint32_t clk_n_val) +static void uart_lpss_init(uintptr_t baseaddr) +{ + /* Take UART out of reset */ + lpss_reset_release(baseaddr); + + /* Set M and N divisor inputs and enable clock */ + lpss_clk_update(baseaddr, CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL, + CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL); +} + +void uart_common_init(device_t dev, uintptr_t baseaddr) { /* Set UART base address */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); @@ -29,11 +38,8 @@ void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val, pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - /* Take UART out of reset */ - lpss_reset_release(baseaddr); + uart_lpss_init(baseaddr); - /* Set M and N divisor inputs and enable clock */ - lpss_clk_update(baseaddr, clk_m_val, clk_n_val); } #if ENV_RAMSTAGE |