soc/intel/common: Clean up PMC library GPE handling API

1. Update gpe handling function names to explicitly mention if they
are operating on:
 a. STD GPE events
 b. GPIO GPE events
 c. Both
2. Update comment block in pmclib.h to use generic names for STD and
GPIO GPE registers instead of using any one platform specific names.

BUG=b:67712608

Change-Id: I03349fe85ac31d4215418b884afd8c4b531e68d3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21968
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 67 insertions, 58 deletions

diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h
index 05a4a06294..9dbac24f8c 100644
--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h
+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h
@@ -100,40 +100,34 @@ uint32_t soc_reset_tco_status(void);
 /* GPE */
 
 /*
- * We have gpe0a_en/sts, gpe0b_en/sts, gpe0c_en/sts and gpe0d_en/sts
- * registers. gpe0a_en is symmetrical to the general purpose event
- * 0a status register and have all the enable bits for
- * gpe's. Other gpe registers gpe0b_en, gpe0c_en and
- * gpe0d_en are symmetrical to general purpose event status
- * registers and reads/writes to those register will result in
- * the transaction being forwarded to the corresponding GPIO
- * community based on the GPIO_GPE_CFG.gpe0_dw1, GPIO_GPE_CFG.gpe0_dw2
- * and GPIO_GPE_CFG.gpe0_dw3 register configuration.
+ * We have symmetrical pairs of GPE0_EN/STS registers for Standard(STD) and GPIO
+ * events. STD events are specific to SoC and one of the GPE0_EN/STS pairs
+ * handles the STD events. Other GPE0_EN/STS pairs are used for GPIO events
+ * based on the GPE0_DWx mappings.
  *
  * STS registers are symmetrical to event enable registers.
- * For gpe0a_sts register if the corresponding _EN bit is set in gpe0a_en,
- * then when the STS bit get set, the PMC will generate a Wake Event.
- * Once back in an S0 state (or if already in an S0 state when the event
+ * In case of STD events, for GPE0_STS register if the corresponding _EN bit is
+ * set in GPE0_EN, then when the STS bit gets set, the PMC will generate a Wake
+ * Event. Once back in an S0 state (or if already in an S0 state when the event
  * occurs), the PMC will also generate an SCI if the SCI_EN bit is set,
- * or an SMI# if the SCI_EN bit is not set. Other gpe registers gpe0b_sts,
- * gpe0c_sts and gpe0d_sts are symmetrical to general purpose event enable
- * registers and reads/writes to those register will result in
- * the transaction being forwarded to the corresponding GPIO
- * community based on the GPIO_GPE_CFG.gpe0_dw1, GPIO_GPE_CFG.gpe0_dw2 and
- * GPIO_GPE_CFG.gpe0_dw3 register configuration.
- */
-/* Enable a standard GPE in gpe0_en register */
-void pmc_enable_gpe(uint32_t mask);
-/* Disable a standard GPE in gpe0a_en register */
-void pmc_disable_gpe(uint32_t mask);
-/* Disable all GPE's in gpe0a_en register */
+ * or an SMI# if the SCI_EN bit is not set.
+ *
+ * GPIO GPE registers are symmetrical to STD GPE registers and reads/writes to
+ * those register will result in the transaction being forwarded to the
+ * corresponding GPIO community based on the GPIO_GPE_CFG.gpe0_dwX register
+ * configuration.
+ */
+/* Enable a standard GPE. */
+void pmc_enable_std_gpe(uint32_t mask);
+/* Disable a standard GPE. */
+void pmc_disable_std_gpe(uint32_t mask);
+/* Disable all GPE's in STD and GPIO GPE registers. */
 void pmc_disable_all_gpe(void);
-/* Clear all GPE status and return "standard" GPE event status */
-uint32_t pmc_clear_gpe_status(void);
+/* Clear STD and GPIO GPE status registers. */
+void pmc_clear_all_gpe_status(void);
+
 /* Clear status bits in Power and Reset Status (PRSTS) register */
-void pmc_clear_status(void);
-/* Clear the gpio gpe0 status bits in ACPI registers */
-void pmc_clear_gpi_gpe_sts(void);
+void pmc_clear_prsts(void);
 
 /*
  * Enable or disable global reset. If global reset is enabled, hard reset and
@@ -162,7 +156,7 @@ int pmc_fill_power_state(struct chipset_power_state *ps);
 /*
  * Sets the gpe routing table by properly programming the GPE_CFG
  * and the MISCCFG registers. This function calls soc specific
- * soc_get_gpe_configs which reads the devicetree info
+ * soc_get_gpi_gpe_configs which reads the devicetree info
  * and populates the dw variables and also returns the bit offset
  * in GPIO_CFG register which is assigned to ACPI register.
  */
@@ -182,17 +176,17 @@ const char * const *soc_smi_sts_array(size_t *a);
 
 /*
  * This function returns array of string which represents
- * names for the General purpose Event status register bits.
+ * names for the STD GPE status register bits.
  * Size of the array is returned as an output parameter.
  */
-const char * const *soc_gpe_sts_array(size_t *a);
+const char * const *soc_std_gpe_sts_array(size_t *a);
 
 /*
  * This function gets the gpe0 dwX values from devicetree
  * for pmc_gpe_init which will use those to set the GPE_CFG
  * register.
  */
-void soc_get_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2);
+void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2);
 
 /*
  * Reads soc specific power management crtitical registers, fills
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index 0afcdb2a2c..6e1d7eec22 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -230,27 +230,39 @@ uint32_t pmc_clear_tco_status(void)
 }
 
 /* GPE */
-void pmc_enable_gpe(uint32_t mask)
+static void pmc_enable_gpe(int gpe, uint32_t mask)
 {
-	uint32_t gpe0a_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
-	gpe0a_en |= mask;
-	outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
+	uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe));
+	gpe0_en |= mask;
+	outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe));
 }
 
-void pmc_disable_gpe(uint32_t mask)
+static void pmc_disable_gpe(int gpe, uint32_t mask)
 {
-	uint32_t gpe0a_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
-	gpe0a_en &= ~mask;
-	outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
+	uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe));
+	gpe0_en &= ~mask;
+	outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe));
+}
+
+void pmc_enable_std_gpe(uint32_t mask)
+{
+	pmc_enable_gpe(GPE_STD, mask);
+}
+
+void pmc_disable_std_gpe(uint32_t mask)
+{
+	pmc_disable_gpe(GPE_STD, mask);
 }
 
 void pmc_disable_all_gpe(void)
 {
-	pmc_disable_gpe(~0);
+	int i;
+	for (i = 0; i < GPE0_REG_MAX; i++)
+		pmc_disable_gpe(i, ~0);
 }
 
 /* Clear the gpio gpe0 status bits in ACPI registers */
-void pmc_clear_gpi_gpe_sts(void)
+static void pmc_clear_gpi_gpe_status(void)
 {
 	int i;
 
@@ -263,14 +275,14 @@ void pmc_clear_gpi_gpe_sts(void)
 	}
 }
 
-static uint32_t reset_gpe_status(void)
+static uint32_t reset_std_gpe_status(void)
 {
 	uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD));
 	outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD));
 	return gpe_sts;
 }
 
-static uint32_t print_gpe_sts(uint32_t gpe_sts)
+static uint32_t print_std_gpe_sts(uint32_t gpe_sts)
 {
 	size_t array_size;
 	const char *const *sts_arr;
@@ -278,18 +290,24 @@ static uint32_t print_gpe_sts(uint32_t gpe_sts)
 	if (!gpe_sts)
 		return gpe_sts;
 
-	printk(BIOS_DEBUG, "GPE0a_STS: ");
+	printk(BIOS_DEBUG, "GPE0 STD STS: ");
 
-	sts_arr = soc_gpe_sts_array(&array_size);
+	sts_arr = soc_std_gpe_sts_array(&array_size);
 	print_num_status_bits(array_size, gpe_sts, sts_arr);
 	printk(BIOS_DEBUG, "\n");
 
 	return gpe_sts;
 }
 
-uint32_t pmc_clear_gpe_status(void)
+static void pmc_clear_std_gpe_status(void)
+{
+	print_std_gpe_sts(reset_std_gpe_status());
+}
+
+void pmc_clear_all_gpe_status(void)
 {
-	return print_gpe_sts(reset_gpe_status());
+	pmc_clear_std_gpe_status();
+	pmc_clear_gpi_gpe_status();
 }
 
 __attribute__ ((weak))
@@ -297,7 +315,7 @@ void soc_clear_pm_registers(uintptr_t pmc_bar)
 {
 }
 
-void pmc_clear_status(void)
+void pmc_clear_prsts(void)
 {
 	uint32_t prsts;
 	uintptr_t pmc_bar;
@@ -504,7 +522,7 @@ void pmc_gpe_init(void)
 	/*
 	 * Get the dwX values for pmc gpe settings.
 	 */
-	soc_get_gpe_configs(&dw0, &dw1, &dw2);
+	soc_get_gpi_gpe_configs(&dw0, &dw1, &dw2);
 
 	const uint32_t gpio_cfg_mask =
 	    (GPE0_DWX_MASK << GPE0_DW_SHIFT(0)) |
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 3f1f490861..7821dbaddc 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -151,7 +151,7 @@ void smihandler_southbridge_sleep(
 		elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
 
 	/* Clear pending GPE events */
-	pmc_clear_gpe_status();
+	pmc_clear_all_gpe_status();
 
 	/* Next, do the deed. */
 
@@ -183,9 +183,6 @@ void smihandler_southbridge_sleep(
 		break;
 	}
 
-	/* Clear the gpio gpe0 status bits in ACPI registers */
-	pmc_clear_gpi_gpe_sts();
-
 	/* Tri-state specific GPIOS to avoid leakage during S3/S5 */
 
 	/*
@@ -328,7 +325,7 @@ void smihandler_southbridge_pm1(
 void smihandler_southbridge_gpe0(
 	const struct smm_save_state_ops *save_state_ops)
 {
-	pmc_clear_gpe_status();
+	pmc_clear_all_gpe_status();
 }
 
 void smihandler_southbridge_tco(
diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c
index 8428fca2c7..d5f42a76e6 100644
--- a/src/soc/intel/common/block/smm/smm.c
+++ b/src/soc/intel/common/block/smm/smm.c
@@ -35,7 +35,7 @@ void smm_southbridge_clear_state(void)
 	pmc_clear_smi_status();
 	pmc_clear_pm1_status();
 	pmc_clear_tco_status();
-	pmc_clear_gpe_status();
+	pmc_clear_all_gpe_status();
 }
 
 void smm_southbridge_enable(void)
@@ -43,7 +43,7 @@ void smm_southbridge_enable(void)
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
 	/* Configure events */
 	pmc_enable_pm1(PWRBTN_EN | GBL_EN);
-	pmc_disable_gpe(PME_B0_EN);
+	pmc_disable_std_gpe(PME_B0_EN);
 
 	/*
 	 * Enable SMI generation: