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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2019-11-12 23:35:50 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-18 15:01:09 +0000 |
| commit | 09ea37172eb62d2b675b3d7a1db36c697c49a6da (patch) | |
| tree | f9f18c79991e934e6e5c6b626e0b42d71b091a45 /src/soc/intel/common | |
| parent | 206905c309a6a7643a61633d0563ad1245fe7f93 (diff) | |
| download | coreboot-09ea37172eb62d2b675b3d7a1db36c697c49a6da.tar.xz | |
soc/intel/common: Add function to wait for CSE to enter Soft Temp Disable mode
Below helper function is added:
cse_wait_com_soft_temp_disable() - It polls for CSE's operation mode
'Soft Temporary Disable'. CSE enters this mode when it boots from
RO(BP1) partition. The function must be called after resetting CSE to
wait for CSE to enter 'Soft Temporary Disable' Mode.
BUG=b:145809764
Change-Id: Ibdcf01f31b0310932b8e834ae83144f8a67f1fef
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 23 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 5 |
2 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index afce985fa8..5877d537f8 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -68,6 +68,9 @@ #define MEI_HDR_CSE_ADDR_START 0 #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) +/* Wait up to 5 seconds for CSE to boot from RO(BP1) */ +#define CSE_DELAY_BOOT_TO_RO (5 * 1000) + static struct cse_device { uintptr_t sec_bar; } cse; @@ -304,6 +307,26 @@ uint8_t cse_wait_sec_override_mode(void) return 1; } +/* + * Polls for CSE's current operation mode 'Soft Temporary Disable'. + * The CSE enters the current operation mode when it boots from RO(BP1). + */ +uint8_t cse_wait_com_soft_temp_disable(void) +{ + struct stopwatch sw; + stopwatch_init_msecs_expire(&sw, CSE_DELAY_BOOT_TO_RO); + while (!cse_is_hfs1_com_soft_temp_disable()) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: Timed out waiting for CSE to boot from RO!\n"); + return 0; + } + } + printk(BIOS_SPEW, "HECI: CSE took %lu ms to boot from RO\n", + stopwatch_duration_msecs(&sw)); + return 1; +} + static int wait_heci_ready(void) { struct stopwatch sw; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index af8d85272d..c597a3f46f 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -192,4 +192,9 @@ bool cse_is_hfs1_com_soft_temp_disable(void); */ bool cse_is_hfs3_fw_sku_custom(void); +/* + * Polls for CSE's current operation mode 'Soft Temp Disable'. + * Returns 0 on failure and 1 on success. + */ +uint8_t cse_wait_com_soft_temp_disable(void); #endif // SOC_INTEL_COMMON_CSE_H |