summaryrefslogtreecommitdiff
path: root/src/soc/intel/common
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@google.com>2020-11-05 10:09:07 -0800
committerDuncan Laurie <dlaurie@chromium.org>2020-11-20 00:27:13 +0000
commit15ca9034b39a7fe0d883c0406d3c7591163d33f4 (patch)
tree5262c37e9dcbe58865db6005acbf9b0e37c30c89 /src/soc/intel/common
parent2b3de787a49e4a1ab0e47e9c6ce1115548ed3287 (diff)
downloadcoreboot-15ca9034b39a7fe0d883c0406d3c7591163d33f4.tar.xz
soc/intel/common/block/cse: Clear post code before reset
To avoid "unknown post code 0x55" entries in the event log on cold boot clear the post code before doing the CSE initiated reset. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I68078c04230dbc24f9cc63b1ef5c435055aa1186 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/block/cse/cse.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index ef6db3da4f..d10492bbe0 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -555,6 +555,9 @@ int heci_reset(void)
{
uint32_t csr;
+ /* Clear post code to prevent eventlog entry from unknown code. */
+ post_code(0);
+
/* Send reset request */
csr = read_host_csr();
csr |= (CSR_RESET | CSR_IG);