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authorArthur Heymans <arthur@aheymans.xyz>2019-10-22 21:31:29 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-03-04 16:20:28 +0000
commit6a8cde4927bd6bff60a783c72356fcce801511b8 (patch)
tree44419403a33e4c21a7b907829d8ea35e9e9c497a /src/soc/intel/common
parenteb6887e1b62513e02d2b65c783242d411e8b509c (diff)
downloadcoreboot-6a8cde4927bd6bff60a783c72356fcce801511b8.tar.xz
soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZE
The cache as ram code will use one form of a non-eviction mode. Change-Id: I418eb48434aa3da3bf5ca65315bb8c9077523966 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/block/cpu/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig
index 8cc572d3b2..0882dd8827 100644
--- a/src/soc/intel/common/block/cpu/Kconfig
+++ b/src/soc/intel/common/block/cpu/Kconfig
@@ -21,6 +21,7 @@ config SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
config SOC_INTEL_COMMON_BLOCK_CAR
bool
default n
+ select NO_FIXED_XIP_ROM_SIZE
help
This option allows you to select how cache-as-ram (CAR) is set up.