diff options
| author | Robbie Zhang <robbie.zhang@intel.com> | 2017-02-21 14:00:31 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-23 19:57:17 +0100 |
| commit | 7de031759b916bbb91e74e6eea371b5ca87e6bd5 (patch) | |
| tree | 3a21679ac510c4fb68f88ea8dae4cd1537231ff6 /src/soc/intel/common | |
| parent | 08d808ff3d2f4ed373fd7390cbf16a63bbe6a7d5 (diff) | |
| download | coreboot-7de031759b916bbb91e74e6eea371b5ca87e6bd5.tar.xz | |
soc/intel/skylake: Add SGX initialization
This patch implements SGX initialization steps in coreboot per Intel SGX
BWG rev 2.0.8 for Kaby Lake SoC. If enabled on a Kabylake device, SoC
capability and PRM (processor reserved memory) of desired size (needs to
be configured through PrmrrSize) are provisioned for later software
stack to use SGX (i.e., run SGX enclaves).
One issue is still puzzling and needs to be addressed: by calling
configure_sgx() in cpu_core_init() which is the per-thread function, SGX
is always failing for thread 0 but is successful for other 3 threads.
I had to call configure_sgx() again from soc_init_cpus() which is the
BSP-only function to make it enable on the BSP.
Another pending work is the implementation for the Owner Epoch update
which shall be added later.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified SGX activation is successful on all threads.
Change-Id: I8b64284875eae061fa8e7a01204d48d320a285a9
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/18445
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 32fd5a13e5..119c21526c 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -40,6 +40,7 @@ #define MSR_FEATURE_CONFIG 0x13c #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL #define FEATURE_CONFIG_LOCK (1 << 0) +#define IA32_MCG_CAP 0x179 #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) @@ -57,6 +58,7 @@ #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_POWER_CTL 0x1fc #define MSR_EVICT_CTL 0x2e0 +#define IA32_MC0_CTL 0x400 #define IA32_MC0_STATUS 0x401 #define SMM_FEATURE_CONTROL_MSR 0x4e0 #define SMM_CPU_SAVE_EN (1 << 1) |