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authorSridhar Siricilla <sridhar.siricilla@intel.com>2019-09-23 20:59:38 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-02-09 19:19:46 +0000
commit8e4654527ef5fec658ca5aacad0612653d3dcf30 (patch)
tree5cf7d9519334074506d31e0e3fbc446457fe4463 /src/soc/intel/common
parent6d5f007813f6a2ffbdd6a633f31d207672eee2e1 (diff)
downloadcoreboot-8e4654527ef5fec658ca5aacad0612653d3dcf30.tar.xz
soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoC
Below changes are implemented: 1. Move HFSTS1 register definition to SoC since HFSTS1 register definition is specific to a SoC. Moving structure back to SoC specific to avoid unnecessay SoC specific macros in the common code. 2. Define a set of APIs in common code since CSE operation modes and working states are same across SoCs. cse_is_hfs1_com_normal(void) cse_is_hfs1_com_secover_mei_msg(void) cse_is_hfs1_com_soft_temp_disable(void) cse_is_hfs1_cws_normal(void) 3. Modify existing code to use callbacks to get data of me_hfs1 structure. TEST=Build and Boot hatch, soraka, tglrvp, bobba and iclrvp boards. Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/block/cse/cse.c44
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cse.h48
2 files changed, 54 insertions, 38 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 4b9d1a4030..440b59b819 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -24,6 +24,7 @@
#include <intelblocks/cse.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
+#include <soc/me.h>
#include <string.h>
#include <timer.h>
@@ -238,17 +239,35 @@ static int cse_ready(void)
return csr & CSR_READY;
}
-/*
- * Checks if CSE is in ME_HFS1_COM_SECOVER_MEI_MSG operation mode. This is the mode where
- * CSE will allow reflashing of CSE region.
- */
-static uint8_t check_cse_sec_override_mode(void)
+static bool cse_check_hfs1_com(int mode)
{
union me_hfsts1 hfs1;
hfs1.data = me_read_config32(PCI_ME_HFSTS1);
- if (hfs1.fields.operation_mode == ME_HFS1_COM_SECOVER_MEI_MSG)
- return 1;
- return 0;
+ return hfs1.fields.operation_mode == mode;
+}
+
+bool cse_is_hfs1_cws_normal(void)
+{
+ union me_hfsts1 hfs1;
+ hfs1.data = me_read_config32(PCI_ME_HFSTS1);
+ if (hfs1.fields.working_state == ME_HFS1_CWS_NORMAL)
+ return true;
+ return false;
+}
+
+bool cse_is_hfs1_com_normal(void)
+{
+ return cse_check_hfs1_com(ME_HFS1_COM_NORMAL);
+}
+
+bool cse_is_hfs1_com_secover_mei_msg(void)
+{
+ return cse_check_hfs1_com(ME_HFS1_COM_SECOVER_MEI_MSG);
+}
+
+bool cse_is_hfs1_com_soft_temp_disable(void)
+{
+ return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE);
}
/* Makes the host ready to communicate with CSE */
@@ -266,7 +285,7 @@ uint8_t wait_cse_sec_override_mode(void)
{
struct stopwatch sw;
stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY);
- while (!check_cse_sec_override_mode()) {
+ while (!cse_is_hfs1_com_secover_mei_msg()) {
udelay(HECI_DELAY);
if (stopwatch_expired(&sw))
return 0;
@@ -632,18 +651,15 @@ int send_hmrfpo_enable_msg(void)
struct hmrfpo_enable_resp resp;
size_t resp_size = sizeof(struct hmrfpo_enable_resp);
- union me_hfsts1 hfs1;
printk(BIOS_DEBUG, "HECI: Send HMRFPO Enable Command\n");
- hfs1.data = me_read_config32(PCI_ME_HFSTS1);
/*
* This command can be run only if:
* - Working state is normal and
* - Operation mode is normal or temporary disable mode.
*/
- if (hfs1.fields.working_state != ME_HFS1_CWS_NORMAL ||
- (hfs1.fields.operation_mode != ME_HFS1_COM_NORMAL &&
- hfs1.fields.operation_mode != ME_HFS1_COM_SOFT_TEMP_DISABLE)) {
+ if (!cse_is_hfs1_cws_normal() ||
+ (!cse_is_hfs1_com_normal() && !cse_is_hfs1_com_soft_temp_disable())) {
printk(BIOS_ERR, "HECI: ME not in required Mode\n");
goto failed;
}
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 515f1a47d5..46730707c8 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -51,30 +51,6 @@ enum {
PCI_ME_HFSTS6 = 0x6C,
};
-/* ME Host Firmware Status register 1 */
-union me_hfsts1 {
- u32 data;
- struct {
- u32 working_state: 4;
- u32 mfg_mode: 1;
- u32 fpt_bad: 1;
- u32 operation_state: 3;
- u32 fw_init_complete: 1;
- u32 ft_bup_ld_flr: 1;
- u32 update_in_progress: 1;
- u32 error_code: 4;
- u32 operation_mode: 4;
- u32 reset_count: 4;
- u32 boot_options_present: 1;
- u32 reserved1: 1;
- u32 bist_test_state: 1;
- u32 bist_reset_request: 1;
- u32 current_power_source: 2;
- u32 d3_support_valid: 1;
- u32 d0i3_support_valid: 1;
- } __packed fields;
-};
-
/* HECI Message Header */
struct mkhi_hdr {
uint8_t group_id;
@@ -172,4 +148,28 @@ int send_hmrfpo_get_status_msg(void);
#define MKHI_HMRFPO_LOCKED 1
#define MKHI_HMRFPO_ENABLED 2
+/*
+ * Checks current working operation state is normal or not.
+ * Returns true if CSE's current working state is normal, otherwise false.
+ */
+bool cse_is_hfs1_cws_normal(void);
+
+/*
+ * Checks CSE's current operation mode is normal or not.
+ * Returns true if CSE's current operation mode is normal, otherwise false.
+ */
+bool cse_is_hfs1_com_normal(void);
+
+/*
+ * Checks CSE's current operation mode is SECOVER_MEI_MSG or not.
+ * Returns true if CSE's current operation mode is SECOVER_MEI_MSG, otherwise false.
+ */
+bool cse_is_hfs1_com_secover_mei_msg(void);
+
+/*
+ * Checks CSE's current operation mode is Soft Disable Mode or not.
+ * Returns true if CSE's current operation mode is Soft Disable Mode, otherwise false.
+ */
+bool cse_is_hfs1_com_soft_temp_disable(void);
+
#endif // SOC_INTEL_COMMON_CSE_H