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authorElyes HAOUAS <ehaouas@noos.fr>2018-12-18 10:24:55 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-07 10:27:32 +0000
commitf212cf3506a9ad3d699a4afe148bfd554932f7b8 (patch)
tree86f810f53d78c9f1e368f4e75d3991158cec2fcf /src/soc/intel/common
parent844eda0f3b69e8b724fdf14fc663f808f686037f (diff)
downloadcoreboot-f212cf3506a9ad3d699a4afe148bfd554932f7b8.tar.xz
soc/intel: Standardize names of common MSRs
Use defined name in Intel 64 and IA-32 Architectures Software Developer’s Manual. Renamed MSRs are (register address, register name): 0x35 MSR_CORE_THREAD_COUNT 0x121 MSR_EMULATE_PM_TIMER 0x1f4 MSR_PRMRR_PHYS_BASE 0x1f5 MSR_PRMRR_PHYS_MASK 0x2f4 MSR_UNCORE_PRMRR_PHYS_BASE 0x2f5 MSR_UNCORE_PRMRR_PHYS_MASK Change-Id: I53f11a2ce831456d598aa21303a817d18ac89bba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/msr.h6
-rw-r--r--src/soc/intel/common/block/sgx/sgx.c12
2 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 622eb071fb..6fdf26e202 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -33,7 +33,7 @@
#define MSR_POWER_MISC 0x120
#define ENABLE_IA_UNTRUSTED (1 << 6)
#define FLUSH_DL1_L2 (1 << 8)
-#define MSR_EMULATE_PM_TMR 0x121
+#define MSR_EMULATE_PM_TIMER 0x121
#define EMULATE_DELAY_OFFSET_VALUE 20
#define EMULATE_PM_TMR_EN (1 << 16)
#define EMULATE_DELAY_VALUE 0x13
@@ -60,8 +60,8 @@
#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7)
#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12)
#define MSR_TURBO_RATIO_LIMIT 0x1ad
-#define PRMRR_PHYS_BASE_MSR 0x1f4
-#define PRMRR_PHYS_MASK_MSR 0x1f5
+#define MSR_PRMRR_PHYS_BASE 0x1f4
+#define MSR_PRMRR_PHYS_MASK 0x1f5
#define PRMRR_PHYS_MASK_LOCK (1 << 10)
#define PRMRR_PHYS_MASK_VALID (1 << 11)
#define MSR_POWER_CTL 0x1fc
diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c
index 6050dec093..3a4a533280 100644
--- a/src/soc/intel/common/block/sgx/sgx.c
+++ b/src/soc/intel/common/block/sgx/sgx.c
@@ -83,7 +83,7 @@ void prmrr_core_configure(void)
if (!soc_sgx_enabled() || !is_sgx_supported())
return;
- msr = rdmsr(PRMRR_PHYS_MASK_MSR);
+ msr = rdmsr(MSR_PRMRR_PHYS_MASK);
/* If it is locked don't attempt to write PRMRR MSRs. */
if (msr.lo & PRMRR_PHYS_MASK_LOCK)
return;
@@ -109,19 +109,19 @@ void prmrr_core_configure(void)
* - Clear the valid bit in PRMRR mask MSR
* - Lock PRMRR MASK MSR */
prmrr_base.data32.lo |= MTRR_TYPE_WRBACK;
- wrmsr(PRMRR_PHYS_BASE_MSR, (msr_t) {.lo = prmrr_base.data32.lo,
+ wrmsr(MSR_PRMRR_PHYS_BASE, (msr_t) {.lo = prmrr_base.data32.lo,
.hi = prmrr_base.data32.hi});
prmrr_mask.data32.lo &= ~PRMRR_PHYS_MASK_VALID;
prmrr_mask.data32.lo |= PRMRR_PHYS_MASK_LOCK;
- wrmsr(PRMRR_PHYS_MASK_MSR, (msr_t) {.lo = prmrr_mask.data32.lo,
+ wrmsr(MSR_PRMRR_PHYS_MASK, (msr_t) {.lo = prmrr_mask.data32.lo,
.hi = prmrr_mask.data32.hi});
}
static int is_prmrr_set(void)
{
msr_t prmrr_base, prmrr_mask;
- prmrr_base = rdmsr(PRMRR_PHYS_BASE_MSR);
- prmrr_mask = rdmsr(PRMRR_PHYS_MASK_MSR);
+ prmrr_base = rdmsr(MSR_PRMRR_PHYS_BASE);
+ prmrr_mask = rdmsr(MSR_PRMRR_PHYS_MASK);
/* If PRMRR base is zero and PRMRR mask is locked
* then PRMRR is not set */
@@ -191,7 +191,7 @@ static void activate_sgx(void)
static int is_prmrr_approved(void)
{
msr_t msr;
- msr = rdmsr(PRMRR_PHYS_MASK_MSR);
+ msr = rdmsr(MSR_PRMRR_PHYS_MASK);
if (msr.lo & PRMRR_PHYS_MASK_VALID) {
printk(BIOS_INFO, "SGX: MCHECK approved SGX PRMRR\n");
return 1;