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| author | Furquan Shaikh <furquan@google.com> | 2020-05-15 18:52:35 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-17 04:07:16 +0000 |
| commit | 17b48033819976405ce0acd8a8a371f166e576b5 (patch) | |
| tree | a82b2d2fbc634a9acb0722a2fbc796a869fbb265 /src/soc/intel/common | |
| parent | edf2c8eb557c8ee16e72a2177985463e66e194c9 (diff) | |
| download | coreboot-17b48033819976405ce0acd8a8a371f166e576b5.tar.xz | |
soc/intel/common/block/acpi: Mask lower 20 bits of TOLUD
Lower 20bits of TOLUD register include 19 reserved bits and 1 lock
bit. If lock bit is set, then northbridge.asl was reporting the base
address of low MMIO incorrectly i.e. off by 1. This resulted in Linux
kernel complaining that the MMIO window allocated to the device at the
base of low MMIO is incorrect:
pci 0000:00:1c.0: can't claim BAR 8 [mem 0x7fc00000-0x7fcfffff]: no compatible brw
pci 0000:00:1c.0: [mem 0x7fc00000-0x7fcfffff] clipped to [mem 0x7fc00001-0x7fcfff]
pci 0000:00:1c.0: bridge window [mem 0x7fc00001-0x7fcfffff]
This change masks the lower 20 bits of TOLUD register when exposing it
in the ACPI tables to ensure that the base address of low MMIO region
is reported correctly.
TEST=Verified that kernel dmesg no longer complains about the BAR at
base of low MMIO.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4849367d5fa03d70c50dc97c7e84454a65d1887a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41455
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/acpi/acpi/northbridge.asl | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 1f58dfe720..53b21881ae 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -182,8 +182,10 @@ Method (_CRS, 0, Serialized) /* * Fix up PCI memory region * Start with Top of Lower Usable DRAM + * Lower 20 bits of TOLUD register need to be masked since they contain lock and + * reserved bits. */ - PMIN = \_SB.PCI0.MCHC.TLUD + PMIN = \_SB.PCI0.MCHC.TLUD & (0xfff << 20) PLEN = PMAX - PMIN + 1 /* Patch PM02 range based on Memory Size */ |