summaryrefslogtreecommitdiff
path: root/src/soc/intel/common
diff options
context:
space:
mode:
authorMartin Roth <martinroth@google.com>2017-10-16 16:11:05 -0600
committerMartin Roth <martinroth@google.com>2017-10-20 17:48:56 +0000
commit296004315507e75e912276fb6928093b6d6d3ef8 (patch)
treeeb6d1c75c5ca7f7a3311aeea2fc5a47a8fd6a865 /src/soc/intel/common
parent7eb363c505f26aa8cc0a30f5b6c0229ca8914489 (diff)
downloadcoreboot-296004315507e75e912276fb6928093b6d6d3ef8.tar.xz
soc/amd/common: Set AltImageBasePtr to 0
In the original AGESA headers, AltImageBasePtr is a UINT32, so don't set it to VOID. 0 works for either UINT32 or VOID *, as demonstrated by the other 7 places in this file where it's already set to 0 instead of NULL. Change this location to 0 to support either version of the headers. BUG=b:64766233 TEST=Build in cros tree and upstream coreboot, with old headers and updated headers. Change-Id: Ib6f3883e08231a6ca896c2ee2ef631c77feafedd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/common')
0 files changed, 0 insertions, 0 deletions