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authorNaresh G Solanki <naresh.solanki@intel.com>2017-09-27 14:21:18 +0530
committerMartin Roth <martinroth@google.com>2017-10-16 00:16:53 +0000
commitf329f0c3af07793facfbe4b4eb4892f919eaf908 (patch)
tree188c7ad6cffca5d79a450e43330b03f303e10ec6 /src/soc/intel/common
parent71517788470e24e864877ba62cdebec95957f39a (diff)
downloadcoreboot-f329f0c3af07793facfbe4b4eb4892f919eaf908.tar.xz
intel/common: CAR setup CQOS
Enable CQOS on Geminilake. In Apololake, CBM_LEN is 0x7. Whereas the same in Geminilake is 0xF. Thus get CBM_LEN using cpuid instruction & generate CBM_LEN_MASK. Later use the CBM_LEN_MASK when writing to IA32_L2_MASK_* to set right bits. BUG=None TEST= Build for Geminilake platform i.e., glkrvp & check for successful CAR setup. Even verified the same on APL platform i.e., on Reef Change-Id: Ic736dba1a46629ff5bf3183082799c0c1468e6d9 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com Reviewed-on: https://review.coreboot.org/21701 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/block/cpu/car/cache_as_ram.S31
1 files changed, 28 insertions, 3 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 94e269446b..1798de5117 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -255,6 +255,24 @@ car_nem:
.global car_cqos
car_cqos:
/*
+ * Create CBM_LEN_MASK based on CBM_LEN
+ * Get CPUID.(EAX=10H, ECX=2H):EAX.CBM_LEN[bits 4:0]
+ */
+ mov $0x10, %eax
+ mov $0x2, %ecx
+ cpuid
+ and $0x1F, %eax
+ add $1, %al
+
+ mov $1, %ebx
+ mov %al, %cl
+ shl %cl, %ebx
+ sub $1, %ebx
+
+ /* Store the CBM_LEN_MASK in mm3 for later use. */
+ movd %ebx, %mm3
+
+ /*
* Disable both L1 and L2 prefetcher. For yet-to-understood reason,
* prefetchers slow down filling cache with rep stos in CQOS mode.
*/
@@ -284,7 +302,7 @@ car_cqos:
/* Set this mask for initial cache fill */
mov $MSR_L2_QOS_MASK(0), %ecx
rdmsr
- mov %bl, %al
+ mov %ebx, %eax
wrmsr
/* Set CLOS selector to 0 */
@@ -297,8 +315,15 @@ car_cqos:
mov $MSR_L2_QOS_MASK(1), %ecx
rdmsr
/* Invert bits that are to be used for cache */
- mov %bl, %al
- xor $~0, %al /* invert 8 bits */
+ mov %ebx, %eax
+ xor $~0, %eax /* invert 32 bits */
+
+ /*
+ * Use CBM_LEN_MASK stored in mm3 to set bits based on Capacity Bit
+ * Mask Length.
+ */
+ movd %mm3, %ebx
+ and %ebx, %eax
wrmsr
post_code(0x26)