summaryrefslogtreecommitdiff
path: root/src/soc/intel/common
diff options
context:
space:
mode:
authorMeera Ravindranath <meera.ravindranath@intel.com>2020-02-13 13:55:42 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-02-19 12:11:26 +0000
commitf71c6ae216bb493275a4b6a20577c883f7575ca0 (patch)
tree5d2e9ec450ec7861e7873105015414d966194730 /src/soc/intel/common
parent5efe122b2776f168c5aa02cd91f56052608b1220 (diff)
downloadcoreboot-f71c6ae216bb493275a4b6a20577c883f7575ca0.tar.xz
soc/tigerlake: Add IRQ header and ACPI support for JSP
Tigerlake irq.h and pci_irqs.asl have differences compared to Jasperlake. Hence renaming irq.h as irq_tgl.h and pci_irqs.asl as pci_irqs_tgl.asl Also adding a new file irq_jsl.h and pci_irqs_jsl.asl for Jasperlake SoC and allowing irq.h and pci_irqs.asl to choose the correct file based on SoC selected. BUG=None BRANCH=None TEST=Compilation for Jasperlake board is working Change-Id: Ia8e88f92929fe40d7be1c28947e005cb0d862fcb Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/soc/intel/common')
0 files changed, 0 insertions, 0 deletions