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authorAaron Durbin <adurbin@chromium.org>2017-04-19 10:02:27 -0500
committerAaron Durbin <adurbin@chromium.org>2017-04-24 22:03:13 +0200
commit9d9a121fa0cc0a5b303aaf377ce2a8e426ef0d3a (patch)
tree8130661a121e39da3e0241a3760b0f57ad250824 /src/soc/intel/common
parent8bc896f7129b8e47cbca1c15b87a449620186cf8 (diff)
downloadcoreboot-9d9a121fa0cc0a5b303aaf377ce2a8e426ef0d3a.tar.xz
soc/intel/common: provide default tis_plat_irq_status() implementation
On Intel platforms utilizing the CR50 TPM the interrupts are routed to GPIOs connected to the GPE blocks. Therefore, provide a common implementation for tis_plat_irq_status() to reduce code duplication. This code could be further extended to not be added based on MAINBOARD_HAS_TPM_CR50, but that's all that's using it for now. Change-Id: I955df0a536408b2ccd07146893337c53799e243f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19369 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/Kconfig6
-rw-r--r--src/soc/intel/common/Makefile.inc5
-rw-r--r--src/soc/intel/common/tpm_tis.c22
3 files changed, 33 insertions, 0 deletions
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 919cb50406..7612850965 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -130,4 +130,10 @@ config SOC_INTEL_COMMON_NHLT
bool
default n
+config TPM_TIS_ACPI_INTERRUPT
+ int
+ help
+ acpi_get_gpe() is used to provide interrupt status to TPM layer.
+ This option specifies the GPE number.
+
endif # SOC_INTEL_COMMON
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index acfd0548b2..b01fc8a70e 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -37,6 +37,11 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c
smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c
+bootblock-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c
+verstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c
+romstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c
+ramstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c
+
# Create and add the MRC cache to the cbfs image
ifneq ($(CONFIG_CHROMEOS),y)
$(obj)/mrc.cache: $(obj)/config.h
diff --git a/src/soc/intel/common/tpm_tis.c b/src/soc/intel/common/tpm_tis.c
new file mode 100644
index 0000000000..ed57cef488
--- /dev/null
+++ b/src/soc/intel/common/tpm_tis.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <tpm.h>
+
+int tis_plat_irq_status(void)
+{
+ return acpi_get_gpe(CONFIG_TPM_TIS_ACPI_INTERRUPT);
+}