diff options
| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2017-12-27 13:48:58 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-02-07 01:48:07 +0000 |
| commit | f43adf0b894e916f0403761ecb9147d7061b0619 (patch) | |
| tree | 3e0b7cd2e98b50ebefe09788d0c8823175c1649d /src/soc/intel/common | |
| parent | acc2a4819c44b2f111eed64f329ae54db7ff9489 (diff) | |
| download | coreboot-f43adf0b894e916f0403761ecb9147d7061b0619.tar.xz | |
intel/common/block/cpu: Change post_cpus_init after BS_DEV RESOURCES
This patch changes the sequence of post_cpus_init() function of mp_init
to very last of the stages, i.e., ON_EXIT of BS_WRITE_TABLES for normal
boot path, and to ON_ENTRY of BS_OS_RESUME for S3 Resume path.
Also, the fast_spi_cache_bios_region() call inside post_cpus_init()
function is left out, since caching the SPI Bios region is not required
now at this stage.
BUG=none
BRANCH=none
TEST=Build and boot in Soraka (KBL), executed stability tests on multiple
systems.
Change-Id: I97c4a4096a3529a21bae6f2cf5aac654523a5b22
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/23540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/cpu/mp_init.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index ebd55b5188..085a34052e 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -135,14 +135,10 @@ static void post_cpus_init(void *unused) if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0) printk(BIOS_ERR, "MTRR programming failure\n"); - /* Temporarily cache the memory-mapped boot media. */ - if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) && - IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) - fast_spi_cache_bios_region(); - x86_mtrr_check(); } /* Do CPU MP Init before FSP Silicon Init */ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, init_cpus, NULL); -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, post_cpus_init, NULL); +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, post_cpus_init, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, post_cpus_init, NULL); |