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author | Mariusz Szafranski <mariuszx.szafranski@intel.com> | 2017-08-02 17:28:17 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2017-09-05 13:39:54 +0000 |
commit | a404133547c98094a326f60b83e1576ba94b8c06 (patch) | |
tree | 59847d084c0462833878627491cfbf3e67fca4af /src/soc/intel/denverton_ns/acpi/northcluster.asl | |
parent | 84c4987eae9f8686e6d92e38ee18744d69576f2d (diff) | |
download | coreboot-a404133547c98094a326f60b83e1576ba94b8c06.tar.xz |
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC
This change adds support for Intel Atom C3000 SoC
("Denverton" and "Denverton-NS").
Code is partially based on Apollo Lake/Skylake code.
Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Diffstat (limited to 'src/soc/intel/denverton_ns/acpi/northcluster.asl')
-rw-r--r-- | src/soc/intel/denverton_ns/acpi/northcluster.asl | 171 |
1 files changed, 171 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl new file mode 100644 index 0000000000..bbfa13313a --- /dev/null +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 - 2009 coresystems GmbH + * Copyright (C) 2014 - 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "../include/soc/iomap.h" + +Name(_HID,EISAID("PNP0A08")) // PCIe +Name(_CID,EISAID("PNP0A03")) // PCI + +Name(_ADR, 0) +Name(_BBN, 0) + +Device (MCHC) +{ + Name(_ADR, 0x00000000) // 0:0.0 + + OperationRegion(MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset (0x48), // MCHBAR + MHEN, 1, // Enable + , 13, // + MHBR, 22, // MCHBAR + + Offset (0x60), // PCIe BAR + PXEN, 1, // Enable + PXSZ, 2, // BAR size + , 23, // + PXBR, 10, // PCIe BAR + + Offset (0xa8), // Top of Upper Memory + TUUD, 64, + + Offset (0xb8), // TSEGMB + TSEG, 32, + + Offset (0xbc), // Top of Low Used Memory + TLUD, 32, + } +} + +// Current Resource Settings + +Name (MCRS, ResourceTemplate() +{ + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // RAM (0xc0000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000dffff, 0x00000000, + 0x00020000,,, OPR0) + + // PCI Memory Region (Top of memory-PCIEXBAR) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, + 0xfec00000,,, PM01) + +#ifdef ENABLE_TPM + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +#endif + + // PCI Memory Region (TOUUD - 64G) + QWORDMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0x1ffffffff, 0x00000000, + 0x200000000,,, PM02) + +}) // End MCRS + +Method (_CRS, 0, Serialized) +{ + // Find PCI resource area in MCRS + CreateDwordField(MCRS, ^PM01._MIN, PMIN) + CreateDwordField(MCRS, ^PM01._MAX, PMAX) + CreateDwordField(MCRS, ^PM01._LEN, PLEN) + + // MMIO Low is saved in NVS + Store (\MMOB, PMIN) + Store (\MMOL, PMAX) + Add (Subtract (PMAX, PMIN), 1, PLEN) + + // Find PCI resource area in MCRS + CreateQWordField(MCRS, ^PM02._MIN, P2MN) + CreateQWordField(MCRS, ^PM02._MAX, P2MX) + CreateQWordField(MCRS, ^PM02._LEN, P2LN) + + // MMIO High is saved in NVS + Store(\MMHB, P2MN) + Store(\MMHL, P2MX) + Add(Subtract(P2MX,P2MN),1,P2LN) + + Return (MCRS) +} // End _CRS + +/* PCI Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate() { + // PCIEXBAR memory range + Memory32Fixed(ReadOnly, DEFAULT_PCIEXBAR, 0x10000000) + // TSEG + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB) + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + // Fix up 32-bit TSEG + CreateDWordField(PDRS, ^TSMB._BAS, TSMN) + Store(\TSGB, TSMN) + CreateDWordField(PDRS, ^TSMB._LEN, TSLN) + Store(\TSSZ, TSLN) + Return(PDRS) + } +} + +// Global Registers +Device (GREG) { + Name (_ADR, 0x00040000) +} + +// Root Complex Event Collector +Device (RCEC) { + Name (_ADR, 0x00050000) +} + +// Virtual root port 2 +Device (VRP2) { + Name (_ADR, 0x00060000) +} |