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| author | Julien Viard de Galbert <jviarddegalbert@online.net> | 2018-03-05 11:10:16 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-03-09 12:57:54 +0000 |
| commit | 546923f906308a737d7797cb96f183a121ab4e10 (patch) | |
| tree | 333feac6b65abce3b0bf7571b73ab8f4d3cb11d5 /src/soc/intel/denverton_ns/bootblock/uart.c | |
| parent | 7b37668650f8ee13ace646dc98584074992a696f (diff) | |
| download | coreboot-546923f906308a737d7797cb96f183a121ab4e10.tar.xz | |
soc/intel/denverton_ns: Update UART legacy mode to keep FSP traces
The FSP can only output its traces when the HSUART PCI device is
available.
- Move the hiding to after last FSP call.
- Adapt coreboot PCI enumeration to keep the legacy configuration.
With UART configured as legacy Linux will not re-enumerate it but detects
it as legacy (ttyS0 instead of ttyS4).
Change-Id: Id8801e178ffd8eeee78ece07da7bd6b8dbd88538
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/denverton_ns/bootblock/uart.c')
| -rw-r--r-- | src/soc/intel/denverton_ns/bootblock/uart.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c index affddbaec2..9af42ee217 100644 --- a/src/soc/intel/denverton_ns/bootblock/uart.c +++ b/src/soc/intel/denverton_ns/bootblock/uart.c @@ -65,15 +65,6 @@ static void pci_early_hsuart_device_probe(u8 bus, u8 dev, u8 func, SIZE_OF_HSUART_RES * func + PSR_OFFSET); *psr_reg >>= 1; #endif - -#if (IS_ENABLED(CONFIG_LEGACY_UART_MODE)) - /* Hide HSUART on PCI to prevent re-enumeration - * and enable legacy mode. - */ - pci_write_config32(uart_dev, PCI_FUNC_RDCFG_HIDE, - pci_read_config32(uart_dev, PCI_FUNC_RDCFG_HIDE) | - 1); -#endif } static void early_config_gpio(void) |