diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-01 08:47:51 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-11 21:06:53 +0000 |
| commit | 419bfbc1f1e7bb40c1e5698e1f50d4e275665d97 (patch) | |
| tree | 8b5a5413e791e15d7e386c958b2a24899d8cddc2 /src/soc/intel/denverton_ns/cpu.c | |
| parent | 603963e1ba4147ef31a72b94304708ab416e3b6a (diff) | |
| download | coreboot-419bfbc1f1e7bb40c1e5698e1f50d4e275665d97.tar.xz | |
src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names.
Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28752
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns/cpu.c')
| -rw-r--r-- | src/soc/intel/denverton_ns/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index b7b5550aaa..676fab7cbd 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -44,9 +44,9 @@ static void denverton_core_init(struct device *cpu) /* Enable speed step. */ if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= SPEED_STEP_ENABLE_BIT; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); } } |