diff options
author | Julien Viard de Galbert <jviarddegalbert@online.net> | 2018-04-05 11:24:45 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-25 11:24:30 +0000 |
commit | cf2b72f951ea6797273ca76958fc15bf147d5ff0 (patch) | |
tree | dcabccc89a60ee0956a153965b60aeee977576b5 /src/soc/intel/denverton_ns/include | |
parent | b933495229ae68f7e539f58dcc52e8a9b4901acc (diff) | |
download | coreboot-cf2b72f951ea6797273ca76958fc15bf147d5ff0.tar.xz |
soc/intel/denverton_ns: Enable ACPI using intelblock
- Port the existing denverton tables to intelblock
- Add C-States table for denverton
Note: Removed code is functionally identical to corresponding
common code.
Tested-on: scaleway/tagada
Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/denverton_ns/include')
-rw-r--r-- | src/soc/intel/denverton_ns/include/soc/acpi.h | 2 | ||||
-rw-r--r-- | src/soc/intel/denverton_ns/include/soc/nvs.h | 5 | ||||
-rw-r--r-- | src/soc/intel/denverton_ns/include/soc/pm.h | 6 | ||||
-rw-r--r-- | src/soc/intel/denverton_ns/include/soc/pmc.h | 11 |
4 files changed, 20 insertions, 4 deletions
diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 14eb167b22..5de58eac67 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -23,12 +23,12 @@ void acpi_create_intel_hpet(acpi_hpet_t *hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); unsigned long southcluster_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp); void southcluster_inject_dsdt(struct device *device); +void motherboard_fill_fadt(acpi_fadt_t *fadt); #endif /* _DENVERTON_NS_ACPI_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h index cf10823ca1..5a94b24bb6 100644 --- a/src/soc/intel/denverton_ns/include/soc/nvs.h +++ b/src/soc/intel/denverton_ns/include/soc/nvs.h @@ -19,7 +19,7 @@ #ifndef _DENVERTON_NS_NVS_H_ #define _DENVERTON_NS_NVS_H_ -typedef struct { +typedef struct global_nvs_t { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -63,9 +63,8 @@ typedef struct { u32 tsegl; /* 0x58 - TSEG Length/Size */ u8 rsvd3[164]; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; -void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index 32d8a76793..09ce1584e5 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -24,6 +24,12 @@ #define GPE_MAX 127 +/* P-state configuration */ +#define PSS_MAX_ENTRIES 15 +#define PSS_RATIO_STEP 1 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + struct chipset_power_state { uint16_t pm1_sts; uint16_t pm1_en; diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index 4db3981d79..f5df21a792 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -38,6 +38,17 @@ #define PMC_ACPI_CNT_SCIS_IRQ21 0x05 #define PMC_ACPI_CNT_SCIS_IRQ22 0x06 #define PMC_ACPI_CNT_SCIS_IRQ23 0x07 + +#define SCI_IRQ_ADJUST 0 +#define SCI_IRQ_SEL (0x07 << SCI_IRQ_ADJUST) +#define SCIS_IRQ9 0x00 +#define SCIS_IRQ10 0x01 +#define SCIS_IRQ11 0x02 +#define SCIS_IRQ20 0x04 +#define SCIS_IRQ21 0x05 +#define SCIS_IRQ22 0x06 +#define SCIS_IRQ23 0x07 + #define PMC_PWRM_BASE 0x48 /* MEM BAR */ #define MASK_PMC_PWRM_BASE 0xfffff000 /* 4K alignment */ #define PMC_GEN_PMCON_A 0xA0 |