diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/soc/intel/denverton_ns/romstage.c | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/denverton_ns/romstage.c')
| -rw-r--r-- | src/soc/intel/denverton_ns/romstage.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 77364b80d2..4477c927e9 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -34,7 +34,7 @@ void __weak mainboard_config_gpios(void) {} -#if IS_ENABLED(CONFIG_DISPLAY_HOBS) +#if CONFIG(DISPLAY_HOBS) static void display_fsp_smbios_memory_info_hob(void) { const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; @@ -141,7 +141,7 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; uintptr_t top_of_ram; -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) void *smm_base; size_t smm_size; uintptr_t tseg_base; @@ -157,7 +157,7 @@ asmlinkage void car_stage_entry(void) fsp_memory_init(false); -#if IS_ENABLED(CONFIG_DISPLAY_HOBS) +#if CONFIG(DISPLAY_HOBS) display_fsp_smbios_memory_info_hob(); #endif @@ -176,7 +176,7 @@ asmlinkage void car_stage_entry(void) /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) /* * Cache the TSEG region at the top of ram. This region is * not restricted to SMM mode until SMM has been relocated. @@ -200,7 +200,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) BL_HSIO_INFORMATION *hsio_config; /* Set the parameters for MemoryInit */ - m_cfg->PcdEnableIQAT = IS_ENABLED(CONFIG_IQAT_ENABLE); + m_cfg->PcdEnableIQAT = CONFIG(IQAT_ENABLE); /* if ME HECI communication is disabled, apply default one*/ if (mupd->FspmConfig.PcdMeHeciCommunication == 0) { |