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| author | Julien Viard de Galbert <jviarddegalbert@online.net> | 2018-11-20 13:47:41 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-24 13:59:14 +0000 |
| commit | ab1227226ebd78b40783cb200e60711b900352f0 (patch) | |
| tree | 7d4e926c30a4089ed044d86dc980c0f49e3236c5 /src/soc/intel/denverton_ns/smm.c | |
| parent | c2540a958b5e8f4ad4ea0db24c408387ae1cb5f8 (diff) | |
| download | coreboot-ab1227226ebd78b40783cb200e60711b900352f0.tar.xz | |
soc/intel/denverton_ns: Rewrite pmutil using pmclib
Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25427
Reviewed-by: David Guckian
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns/smm.c')
| -rw-r--r-- | src/soc/intel/denverton_ns/smm.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index 9d3fa75a6a..65d249911a 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -23,6 +23,7 @@ #include <cpu/x86/smm.h> #include <string.h> +#include <intelblocks/pmclib.h> #include <soc/iomap.h> #include <soc/soc_util.h> #include <soc/pm.h> @@ -48,10 +49,10 @@ void southcluster_smm_clear_state(void) } /* Dump and clear status registers */ - clear_smi_status(); - clear_pm1_status(); - clear_tco_status(); - clear_gpe_status(); + pmc_clear_smi_status(); + pmc_clear_pm1_status(); + pmc_clear_tco_status(); + pmc_clear_all_gpe_status(); clear_pmc_status(); } @@ -60,8 +61,8 @@ void southcluster_smm_enable_smi(void) printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events Disable pcie wake. */ - enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); - disable_gpe(PME_B0_EN); + pmc_enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); + pmc_disable_std_gpe(PME_B0_EN); /* Enable SMI generation: * - on APMC writes (io 0xb2) @@ -71,7 +72,7 @@ void southcluster_smm_enable_smi(void) * - on TCO events * - on microcontroller writes (io 0x62/0x66) */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) |