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author | Mariusz Szafranski <mariuszx.szafranski@intel.com> | 2017-08-02 17:28:17 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2017-09-05 13:39:54 +0000 |
commit | a404133547c98094a326f60b83e1576ba94b8c06 (patch) | |
tree | 59847d084c0462833878627491cfbf3e67fca4af /src/soc/intel/denverton_ns/uart_debug.c | |
parent | 84c4987eae9f8686e6d92e38ee18744d69576f2d (diff) | |
download | coreboot-a404133547c98094a326f60b83e1576ba94b8c06.tar.xz |
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC
This change adds support for Intel Atom C3000 SoC
("Denverton" and "Denverton-NS").
Code is partially based on Apollo Lake/Skylake code.
Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Diffstat (limited to 'src/soc/intel/denverton_ns/uart_debug.c')
-rw-r--r-- | src/soc/intel/denverton_ns/uart_debug.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/uart_debug.c b/src/soc/intel/denverton_ns/uart_debug.c new file mode 100644 index 0000000000..f909d56232 --- /dev/null +++ b/src/soc/intel/denverton_ns/uart_debug.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 - 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <device/pci_def.h> +#include <io.h> +#include <arch/pci_io_cfg.h> +#include <soc/uart.h> + +#define MY_PCI_DEV(SEGBUS, DEV, FN) \ + ((((SEGBUS)&0xFFF) << 20) | (((DEV)&0x1F) << 15) | (((FN)&0x07) << 12)) + +uintptr_t uart_platform_base(int idx); + +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t)pci_io_read_config32( + MY_PCI_DEV(0, CONFIG_HSUART_DEV, idx), + PCI_BASE_ADDRESS_1) + + SIZE_OF_HSUART_RES * idx; +} |