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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-09-17 18:48:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-20 13:35:29 +0000 |
| commit | 43d2527203121be776d3e532c09ca46c2a8afaf9 (patch) | |
| tree | 36f892e7a7d25d04c08e4690b1018db085d88e9e /src/soc/intel/denverton_ns | |
| parent | 8370f6b79c06bcea1a04f53e9028d0aa447e3583 (diff) | |
| download | coreboot-43d2527203121be776d3e532c09ca46c2a8afaf9.tar.xz | |
soc/intel/skylake: lockdown: lock global reset
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only
one (apollolake) is actually calling the code. Add the missing call.
Also fix the register offset in a comment in reset code.
Tested successfully on X11SSM-F by reading ETR3.
Change-Id: If190c3c66889ede105d958b423b38ebdcb698332
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36573
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns')
0 files changed, 0 insertions, 0 deletions