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authorElyes HAOUAS <ehaouas@noos.fr>2020-02-24 13:43:39 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-04 15:43:30 +0000
commit79ccc6933284ca02d17d9e1eda9a531ce43e1f65 (patch)
tree49fe1b78916338575b1a6bec931e2fb885cc311a /src/soc/intel/denverton_ns
parentf3161df2eba8d61445372a9c732c61a1947064bd (diff)
downloadcoreboot-79ccc6933284ca02d17d9e1eda9a531ce43e1f65.tar.xz
src: capitalize 'PCIe'
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/denverton_ns')
-rw-r--r--src/soc/intel/denverton_ns/smm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c
index d05e76bcf9..75f179ec67 100644
--- a/src/soc/intel/denverton_ns/smm.c
+++ b/src/soc/intel/denverton_ns/smm.c
@@ -53,7 +53,7 @@ void smm_southbridge_enable_smi(void)
{
printk(BIOS_DEBUG, "Enabling SMIs.\n");
- /* Configure events Disable pcie wake. */
+ /* Configure events Disable PCIe wake. */
enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
disable_gpe(PME_B0_EN);