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| author | Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> | 2019-01-16 18:07:46 +0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-01-18 04:01:38 +0000 |
| commit | 1e7d69944d3c406bae4c31ac21e7967681f432a6 (patch) | |
| tree | 863ae49f5b1a78e890b613b3a4c74885379878dc /src/soc/intel/denverton_ns | |
| parent | 9cb2da45d8240de73b2a8677f9874ca947d03c11 (diff) | |
| download | coreboot-1e7d69944d3c406bae4c31ac21e7967681f432a6.tar.xz | |
mb/google/sarien/variants/sarien: Adjust TP/TS/H1 I2C CLK to meet spec
After adjustment on Sarien EVT
TouchScreen: 380.7 KHz
TouchPad: 379.3 KHz
H1: 392.2 KHz
BUG=b:122657195
BRANCH=master
TEST=emerge-sarien coreboot chromeos-bootimage
measure by scope
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I0dd92b054d934b38a17898dc8ce9cc18bda1633f
Reviewed-on: https://review.coreboot.org/c/30949
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns')
0 files changed, 0 insertions, 0 deletions