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authorJulien Viard de Galbert <jviarddegalbert@online.net>2018-03-29 14:35:52 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-01-24 14:04:13 +0000
commit15b570b716ff9865fcc942a2c5a0eeeccad1fd1e (patch)
treee33ba581889f8f68f5f7bd19fd8762586a9cb4a7 /src/soc/intel/denverton_ns
parent2f66c709f481aec055809ac30afea094f036a136 (diff)
downloadcoreboot-15b570b716ff9865fcc942a2c5a0eeeccad1fd1e.tar.xz
soc/intel/denverton_ns: Use cpulib in cpu.c
Also remove duplicate code Change-Id: I45da6363a35cf6f5855906bb97ed023681d36df7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25432 Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns')
-rw-r--r--src/soc/intel/denverton_ns/cpu.c10
1 files changed, 1 insertions, 9 deletions
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c
index f954411ff2..b3a12c5cad 100644
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -24,6 +24,7 @@
#include <cpu/intel/turbo.h>
#include <device/device.h>
#include <device/pci.h>
+#include <intelblocks/cpulib.h>
#include <reg_script.h>
#include <soc/msr.h>
@@ -175,15 +176,6 @@ int get_cpu_count(void)
return num_cpus;
}
-static int cpu_config_tdp_levels(void)
-{
- msr_t platform_info;
-
- /* Bits 34:33 indicate how many levels supported */
- platform_info = rdmsr(MSR_PLATFORM_INFO);
- return (platform_info.hi >> 1) & 3;
-}
-
static void set_max_turbo_freq(void)
{
msr_t msr, perf_ctl;