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authorSubrata Banik <subrata.banik@intel.com>2019-10-30 13:32:36 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-11-01 11:49:48 +0000
commit1e8f305957c98cb224574e1fa81938c9a692bd48 (patch)
tree4e8673f3aad87958355af2fdecbb613214d6395e /src/soc/intel/denverton_ns
parent96ca0d93d2309c796eb0d3075fe094a5f500c530 (diff)
downloadcoreboot-1e8f305957c98cb224574e1fa81938c9a692bd48.tar.xz
soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi
This patch creates a common instance of lpc.asl inside intel common code (soc/intel/common/block/acpi/acpi) and asks specific soc code to refer lpc.asl from common code block. Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI rather than LPC. TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify Device(LPCB) device presence after booting to OS. Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36455 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns')
-rw-r--r--src/soc/intel/denverton_ns/acpi/lpc.asl97
-rw-r--r--src/soc/intel/denverton_ns/include/soc/iomap.h2
2 files changed, 5 insertions, 94 deletions
diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl
index cc36451de2..4b6e78698c 100644
--- a/src/soc/intel/denverton_ns/acpi/lpc.asl
+++ b/src/soc/intel/denverton_ns/acpi/lpc.asl
@@ -16,10 +16,11 @@
*/
// Intel LPC Bus Device - 0:1f.0
+#include <soc/intel/common/block/acpi/acpi/lpc.asl>
-Device (LPCB)
+Scope (\_SB.PCI0.LPCB)
{
- Name(_ADR, 0x001f0000)
+ #include "irqlinks.asl"
OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
Field (LPC0, AnyAcc, NoLock, Preserve)
@@ -29,8 +30,6 @@ Device (LPCB)
IOD1, 8,
}
- #include "irqlinks.asl"
-
Device(APIC) // IO APIC
{
Name(_HID,EISAID("PNP0003"))
@@ -40,96 +39,6 @@ Device (LPCB)
})
}
- Device (HPET)
- {
- Name (_HID, EISAID("PNP0103"))
- Name (_CID, 0x010CD041)
-
- Method (_STA, 0) // Device Status
- {
- Return (0xF) // Enable and show device
- }
-
- Name(_CRS, ResourceTemplate()
- {
- Memory32Fixed(ReadOnly, DEFAULT_HPET_ADDR, 0x400)
- })
- }
-
- Device(PIC) // 8259 Interrupt Controller
- {
- Name(_HID,EISAID("PNP0000"))
- Name(_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x20, 0x20, 0x01, 0x02)
- IO (Decode16, 0x24, 0x24, 0x01, 0x02)
- IO (Decode16, 0x28, 0x28, 0x01, 0x02)
- IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
- IO (Decode16, 0x30, 0x30, 0x01, 0x02)
- IO (Decode16, 0x34, 0x34, 0x01, 0x02)
- IO (Decode16, 0x38, 0x38, 0x01, 0x02)
- IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
- IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
- IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
- IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
- IO (Decode16, 0xac, 0xac, 0x01, 0x02)
- IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
- IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
- IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
- IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
- IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
- IRQNoFlags () { 2 }
- })
- }
-
- Device(LDRC) // LPC device: Resource consumption
- {
- Name (_HID, EISAID("PNP0C02"))
- Name (_UID, 2)
- Name (_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
- IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
- IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
- IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x70, 0x70, 0x1, 0x01) // NMI Enable.
- IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
- IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
- //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap
-
- // BIOS ROM shadow memory range
- Memory32Fixed(ReadOnly, 0x000E0000, 0x20000)
-
- // BIOS flash 16MB
- Memory32Fixed(ReadOnly,0xFF000000,0x1000000)
- })
- }
-
- Device (RTC) // Real Time Clock
- {
- Name (_HID, EISAID("PNP0B00"))
- Name (_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x70, 0x70, 1, 8)
-// Disable as Windows doesn't like it, and systems don't seem to use it.
-// IRQNoFlags() { 8 }
- })
- }
-
- Device (TIMR) // Intel 8254 timer
- {
- Name(_HID, EISAID("PNP0100"))
- Name(_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x40, 0x40, 0x01, 0x04)
- IO (Decode16, 0x50, 0x50, 0x10, 0x04)
- IRQNoFlags() {0}
- })
- }
-
Device(IUR3) // Internal UART 1
{
Name(_HID, EISAID("PNP0501"))
diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h
index 8bcef91c2e..c512d55fd0 100644
--- a/src/soc/intel/denverton_ns/include/soc/iomap.h
+++ b/src/soc/intel/denverton_ns/include/soc/iomap.h
@@ -31,6 +31,8 @@
#define ACPI_BASE_ADDRESS DEFAULT_PMBASE
#define DEFAULT_TCO_BASE 0x400
+#define HPET_BASE_ADDRESS 0xfed00000
+
/* Southbridge internal device MEM BARs (Set to match FSP settings) */
#define DEFAULT_PCR_BASE 0xfd000000
#define DEFAULT_PWRM_BASE 0xfe000000