coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

12 files changed, 22 insertions, 22 deletions

diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c
index 7633637950..f3e91ff451 100644
--- a/src/soc/intel/denverton_ns/acpi.c
+++ b/src/soc/intel/denverton_ns/acpi.c
@@ -83,7 +83,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
 	/* Top of Low Memory (start of resource allocation) */
 	gnvs->tolm = top_of_32bit_ram();
 
-#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
+#if CONFIG(CONSOLE_CBMEM)
 	/* Update the mem console pointer. */
 	gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
 #endif
@@ -140,7 +140,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 	u16 pmbase = get_pmbase();
 
 	/* System Management */
-	if (!IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+	if (!CONFIG(HAVE_SMI_HANDLER)) {
 		fadt->smi_cmd = 0x00;
 		fadt->acpi_enable = 0x00;
 		fadt->acpi_disable = 0x00;
diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c
index 110d67d6de..f16ee20620 100644
--- a/src/soc/intel/denverton_ns/bootblock/bootblock.c
+++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c
@@ -58,13 +58,13 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 void bootblock_soc_early_init(void)
 {
 
-#if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+#if (CONFIG(CONSOLE_SERIAL))
 	early_uart_init();
 #endif
 };
 
 void bootblock_soc_init(void)
 {
-	if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE))
+	if (CONFIG(BOOTBLOCK_CONSOLE))
 		printk(BIOS_DEBUG, "FSP TempRamInit successful...\n");
 };
diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c
index 955bf4b936..baa0878f5e 100644
--- a/src/soc/intel/denverton_ns/bootblock/uart.c
+++ b/src/soc/intel/denverton_ns/bootblock/uart.c
@@ -41,7 +41,7 @@ static void pci_early_hsuart_device_probe(u8 bus, u8 dev, u8 func,
 	reg16 = pci_read_config16(uart_dev, PCI_BASE_ADDRESS_0) | mmio_base;
 	pci_write_config16(uart_dev, PCI_BASE_ADDRESS_0, reg16);
 
-#if (IS_ENABLED(CONFIG_NON_LEGACY_UART_MODE))
+#if (CONFIG(NON_LEGACY_UART_MODE))
 	/* Decode MMIO at MEMBA (BAR1) */
 	pci_write_config32(uart_dev, PCI_BASE_ADDRESS_1,
 			   CONFIG_CONSOLE_UART_BASE_ADDRESS +
@@ -53,12 +53,12 @@ static void pci_early_hsuart_device_probe(u8 bus, u8 dev, u8 func,
 	 */
 	pci_write_config16(uart_dev, PCI_COMMAND,
 			   pci_read_config16(uart_dev, PCI_COMMAND) |
-#if (IS_ENABLED(CONFIG_NON_LEGACY_UART_MODE))
+#if (CONFIG(NON_LEGACY_UART_MODE))
 			   PCI_COMMAND_MEMORY |
 #endif
 				   PCI_COMMAND_MASTER | PCI_COMMAND_IO);
 
-#if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_230400))
+#if (CONFIG(CONSOLE_SERIAL_230400))
 	/* Change the highest speed to 230400 */
 	uint32_t *psr_reg =
 		(uint32_t *)(CONFIG_CONSOLE_UART_BASE_ADDRESS +
diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c
index 29bea2b60f..68bd60c83a 100644
--- a/src/soc/intel/denverton_ns/chip.c
+++ b/src/soc/intel/denverton_ns/chip.c
@@ -50,7 +50,7 @@ static struct device_operations cpu_bus_ops = {
 	.enable_resources = DEVICE_NOOP,
 	.init = denverton_init_cpus,
 	.scan_bus = NULL,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 	.acpi_fill_ssdt_generator = generate_cpu_entries,
 #endif
 };
diff --git a/src/soc/intel/denverton_ns/hob_mem.c b/src/soc/intel/denverton_ns/hob_mem.c
index c70c22ad98..e4aa78f291 100644
--- a/src/soc/intel/denverton_ns/hob_mem.c
+++ b/src/soc/intel/denverton_ns/hob_mem.c
@@ -44,7 +44,7 @@ void soc_save_dimm_info(void)
 		return;
 
 	/* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */
-	if (IS_ENABLED(CONFIG_DISPLAY_HOBS))
+	if (CONFIG(DISPLAY_HOBS))
 		soc_display_fsp_smbios_memory_info_hob(memory_info_hob);
 
 	/*
diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h
index f5df21a792..af840a2f1a 100644
--- a/src/soc/intel/denverton_ns/include/soc/pmc.h
+++ b/src/soc/intel/denverton_ns/include/soc/pmc.h
@@ -264,7 +264,7 @@
 
 #if !defined(__ASSEMBLER__) && !defined(__ACPI__)
 
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
 void southcluster_log_state(void);
 #else
 static inline void southcluster_log_state(void) {}
diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c
index c937709255..25d7c9d390 100644
--- a/src/soc/intel/denverton_ns/lpc.c
+++ b/src/soc/intel/denverton_ns/lpc.c
@@ -210,7 +210,7 @@ static void pch_enable_serial_irqs(struct device *dev)
 	/* Set packet length and toggle silent mode bit for one frame. */
 	pci_write_config8(dev, SERIRQ_CNTL,
 			  (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
-#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
+#if !CONFIG(SERIRQ_CONTINUOUS_MODE)
 	pci_write_config8(dev, SERIRQ_CNTL,
 			  (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
 #endif
@@ -310,7 +310,7 @@ void southcluster_enable_dev(struct device *dev)
 static struct device_operations device_ops = {
 	.read_resources = lpc_read_resources,
 	.set_resources = pci_dev_set_resources,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 	.acpi_inject_dsdt_generator = southcluster_inject_dsdt,
 	.write_acpi_tables = southcluster_write_acpi_tables,
 #endif
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c
index 7d623dabf4..514d86d5b5 100644
--- a/src/soc/intel/denverton_ns/memmap.c
+++ b/src/soc/intel/denverton_ns/memmap.c
@@ -51,7 +51,7 @@ u32 top_of_32bit_ram(void)
 /*
  * Add IQAT region size if enabled.
  */
-#if IS_ENABLED(CONFIG_IQAT_ENABLE)
+#if CONFIG(IQAT_ENABLE)
 	iqat_region_size = CONFIG_IQAT_MEMORY_REGION_SIZE;
 #endif
 	return system_agent_region_base(TOLUD) -
diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c
index 193e41c2fc..8b520873e5 100644
--- a/src/soc/intel/denverton_ns/pmc.c
+++ b/src/soc/intel/denverton_ns/pmc.c
@@ -38,7 +38,7 @@ static void pch_power_options(struct device *dev) { /* TODO */ }
 
 static void pch_set_acpi_mode(void)
 {
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
+	if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
 		printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
 		outb(APM_CNT_ACPI_DISABLE, APM_CNT);
 		printk(BIOS_DEBUG, "done.\n");
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index 77364b80d2..4477c927e9 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -34,7 +34,7 @@
 
 void __weak mainboard_config_gpios(void) {}
 
-#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
+#if CONFIG(DISPLAY_HOBS)
 static void display_fsp_smbios_memory_info_hob(void)
 {
 	const FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
@@ -141,7 +141,7 @@ asmlinkage void car_stage_entry(void)
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
 
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
 	void *smm_base;
 	size_t smm_size;
 	uintptr_t tseg_base;
@@ -157,7 +157,7 @@ asmlinkage void car_stage_entry(void)
 
 	fsp_memory_init(false);
 
-#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
+#if CONFIG(DISPLAY_HOBS)
 	display_fsp_smbios_memory_info_hob();
 #endif
 
@@ -176,7 +176,7 @@ asmlinkage void car_stage_entry(void)
 	/* Cache the memory-mapped boot media. */
 	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
 
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
 	/*
 	 * Cache the TSEG region at the top of ram. This region is
 	 * not restricted to SMM mode until SMM has been relocated.
@@ -200,7 +200,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
 	BL_HSIO_INFORMATION *hsio_config;
 
 	/* Set the parameters for MemoryInit */
-	m_cfg->PcdEnableIQAT = IS_ENABLED(CONFIG_IQAT_ENABLE);
+	m_cfg->PcdEnableIQAT = CONFIG(IQAT_ENABLE);
 
 	/* if ME HECI communication is disabled, apply default one*/
 	if (mupd->FspmConfig.PcdMeHeciCommunication == 0) {
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index 9961778321..4d748b2a71 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -209,7 +209,7 @@ static void finalize(void)
 	}
 	finalize_done = 1;
 
-	if (IS_ENABLED(CONFIG_SPI_FLASH_SMM))
+	if (CONFIG(SPI_FLASH_SMM))
 		/* Re-init SPI driver to handle locked BAR */
 		fast_spi_init();
 }
diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c
index ac779d050d..07e07045f5 100644
--- a/src/soc/intel/denverton_ns/uart.c
+++ b/src/soc/intel/denverton_ns/uart.c
@@ -34,7 +34,7 @@ static void dnv_ns_uart_read_resources(struct device *dev)
 {
 	/* read resources to be visible in the log*/
 	pci_dev_read_resources(dev);
-	if (!IS_ENABLED(CONFIG_LEGACY_UART_MODE))
+	if (!CONFIG(LEGACY_UART_MODE))
 		return;
 	struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	if (res == NULL)
@@ -88,6 +88,6 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase)
 {
 	if (phase != END_OF_FIRMWARE)
 		return;
-	if (IS_ENABLED(CONFIG_LEGACY_UART_MODE))
+	if (CONFIG(LEGACY_UART_MODE))
 		hide_hsuarts();
 }