summaryrefslogtreecommitdiff
path: root/src/soc/intel/denverton_ns
diff options
context:
space:
mode:
authorNico Huber <nico.h@gmx.de>2018-05-27 14:01:11 +0200
committerNico Huber <nico.h@gmx.de>2018-05-31 15:11:21 +0000
commit9593e973fa0e3a104837d1df9659b3992d915b34 (patch)
tree8f0aace9603886d215e22c294355a9e5b769133d /src/soc/intel/denverton_ns
parent654cc2fe109ea1be4d22447b3d0e6eb22a75b550 (diff)
downloadcoreboot-9593e973fa0e3a104837d1df9659b3992d915b34.tar.xz
soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)
Boards could choose a high ROM_SIZE that would result in an MTRR config that conflicts with other resources. Thus, always use the filtered CACHE_ROM_SIZE. Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26575 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns')
-rw-r--r--src/soc/intel/denverton_ns/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index 25d7be0d31..7073627a79 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -173,7 +173,7 @@ asmlinkage void car_stage_entry(void)
/* Cache the memory-mapped boot media. */
if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
- postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
MTRR_TYPE_WRPROT);
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
/*