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authorPatrick Rudolph <siro@das-labor.org>2018-10-01 19:17:11 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-22 08:35:32 +0000
commitf677d17ab3cfd1471c0f238a0d32b0d56dd8d37f (patch)
tree9b0c01512de536210262110ac4e7dfb78d6849c1 /src/soc/intel/denverton_ns
parent45022ae056cdbf58429b77daf2da176306312801 (diff)
downloadcoreboot-f677d17ab3cfd1471c0f238a0d32b0d56dd8d37f.tar.xz
intel: Use CF9 reset (part 2)
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also implement board_reset() as a "full reset" (aka. cold reset) as that is what was used here for hard_reset(). Drop soc_reset_prepare() thereby, as it was only used for APL. Also, move the global-reset logic. We leave some comments to remind us that a system_reset() should be enough, where a full_reset() is called now (to retain current behaviour) and looks suspicious. Note, as no global_reset() is implemented for Denverton-NS, we halt there now instead of issuing a non-global reset. This seems safer; a non-global reset might result in a reset loop. Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/denverton_ns')
-rw-r--r--src/soc/intel/denverton_ns/Kconfig1
-rw-r--r--src/soc/intel/denverton_ns/reset.c3
-rw-r--r--src/soc/intel/denverton_ns/romstage.c4
3 files changed, 3 insertions, 5 deletions
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index e22b8ee081..736d567c17 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -33,7 +33,6 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_RESET
select PLATFORM_USES_FSP2_0
- select HAVE_HARD_RESET
select POSTCAR_STAGE
select C_ENVIRONMENT_BOOTBLOCK
select IOAPIC
diff --git a/src/soc/intel/denverton_ns/reset.c b/src/soc/intel/denverton_ns/reset.c
index 97955a574a..577f1c4914 100644
--- a/src/soc/intel/denverton_ns/reset.c
+++ b/src/soc/intel/denverton_ns/reset.c
@@ -15,13 +15,12 @@
#include <console/console.h>
#include <fsp/util.h>
-#include <reset.h>
void chipset_handle_reset(uint32_t status)
{
switch (status) {
case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */
- global_reset();
+ die("Global Reset not implemented!\n");
break;
default:
printk(BIOS_ERR, "unhandled reset type %x\n", status);
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index cf4ae7c1ed..617b64a619 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -15,9 +15,9 @@
*/
#include <cbmem.h>
+#include <cf9_reset.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
-#include <reset.h>
#include <soc/fiamux.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
@@ -93,7 +93,7 @@ static void early_pmc_init(void)
pci_write_config32(dev, PMC_ETR3,
pci_read_config32(dev, PMC_ETR3)
| PMC_ETR3_CF9GR);
- hard_reset();
+ full_reset();
}
}
}