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author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-11 14:05:32 +0200 |
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committer | Nico Huber <nico.h@gmx.de> | 2020-10-24 09:46:45 +0000 |
commit | 10ae1cf2cda38e681849dcc9e6e86ee3330a8b17 (patch) | |
tree | e71fa6148adb9895fbc02111a74a35b395a0794e /src/soc/intel/elkhartlake/cpu.c | |
parent | 29a52c8308ab270c46c1d859db308ba1de5d1e81 (diff) | |
download | coreboot-10ae1cf2cda38e681849dcc9e6e86ee3330a8b17.tar.xz |
{cpu,soc}/intel: deduplicate cpu code
Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl,
tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common.
This change just moves the code. Rework is done in CB:46588.
Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/elkhartlake/cpu.c')
-rw-r--r-- | src/soc/intel/elkhartlake/cpu.c | 41 |
1 files changed, 1 insertions, 40 deletions
diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 271d244db9..c51f3fa550 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> +#include <cpu/intel/common/common.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> @@ -80,29 +81,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void enable_pm_timer_emulation(void) { msr_t msr; @@ -122,23 +100,6 @@ static void enable_pm_timer_emulation(void) wrmsr(MSR_EMULATE_PM_TIMER, msr); } -static void set_energy_perf_bias(u8 policy) -{ - msr_t msr; - int ecx; - - /* Determine if energy efficient policy is supported. */ - ecx = cpuid_ecx(0x6); - if (!(ecx & (1 << 3))) - return; - - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { |