diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2014-06-12 12:38:34 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-06-18 22:11:05 +0200 |
| commit | c0602d4cab34ee228465c2779dda400b367082b6 (patch) | |
| tree | 3d39afeb96d76a5e45561e7b2f940e626f1fe31d /src/soc/intel/fsp_baytrail/Kconfig | |
| parent | c94d73e0e6703369831fe6d489a20d71ab2bb974 (diff) | |
| download | coreboot-c0602d4cab34ee228465c2779dda400b367082b6.tar.xz | |
fsp_baytrail: Add Baytrail B0/B1 "Super SKU" microcode
- Add the Bay Trail B0/B1 microcode. These versions of the SOC were
released as a "Super SKU" which had features of all the different
SKUS (M/D/T/I), and identified as a Bay Trail T as noted by the
number 2 in the third character from the left in the microcode name.
- Update the size of the microcode blob. We should be pushing a patch
to eliminate the need for this shortly.
Change-Id: I57ba51eabe9ea0609ab809f18b95e3bc9d5cb191
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5986
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/Kconfig')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 870147e99c..bce5542e50 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -102,7 +102,7 @@ config CPU_MICROCODE_CBFS_LOC config CPU_MICROCODE_CBFS_LEN hex - default 0xcc00 + default 0x19800 help This should be updated when the microcode patch changes. |