fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip

While similar to the Bay Trail-M/D code based on the MRC, there are
many differences as well:
- Obviously, uses the FSP instead of the MRC binaries.
- FSP does additional hardware setup, so coreboot doesn't need to.
- Different microcode & microcode loading method
- Uses the cache_as_ram.inc from the FSP Driver
- Various other changes in support of the FSP
Additional changes that don't have to to with the FSP vs MRC:
- Updated IRQ Routing
- Different FADT implementation.
This was validated with FSP:
BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
MD5: 9360cd915f0d3e4116bbc782233d7b91

Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5791
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 74 insertions, 0 deletions

diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h
new file mode 100644
index 0000000000..d3a23770dd
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef __SOC_INTEL_FSP_BAYTRAIL_BAYTRAIL_H__
+#define __SOC_INTEL_FSP_BAYTRAIL_BAYTRAIL_H__
+
+#define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS
+#define CPU_MICROCODE_CBFS_LEN 0x26000
+
+/* Southbridge internal device IO BARs (Set to match FSP settings) */
+#define SMBUS_IO_BASE		0xefa0
+#define SMBUS_SLAVE_ADDR	0x24
+#define DEFAULT_GPIOBASE	0x0500
+#define DEFAULT_ABASE		0x0400
+
+/* Southbridge internal device MEM BARs (Set to match FSP settings) */
+#define DEFAULT_IBASE		0xfed08000
+#define DEFAULT_PBASE		0xfed03000
+#define DEFAULT_RCBA		0xfed1c000
+
+/* Everything below this line is ignored in the DSDT */
+#ifndef __ACPI__
+
+/* Device 0:0.0 PCI configuration space (Host Bridge) */
+
+/* SOC types */
+#define SOC_TYPE_BAYTRAIL	0x0F1C
+
+#ifndef __ASSEMBLER__
+static inline void barrier(void) { asm("" ::: "memory"); }
+
+#define SKPAD 0xFC
+
+int bridge_silicon_revision(void);
+void rangeley_early_initialization(void);
+
+#ifndef __PRE_RAM__
+/* soc.c */
+int soc_silicon_revision(void);
+int soc_silicon_type(void);
+int soc_silicon_supported(int type, int rev);
+void soc_enable(device_t dev);
+
+/* debugging functions */
+void print_pci_devices(void);
+void dump_pci_device(unsigned dev);
+void dump_pci_devices(void);
+void dump_spd_registers(void);
+void dump_mem(unsigned start, unsigned end);
+void report_platform_info(void);
+
+#endif	/* __PRE_RAM__ */
+#endif	/* __ASSEMBLER__ */
+
+#endif	/* __ACPI__ */
+#endif