diff options
| author | Mohan D'Costa <mohan@ndr.co.jp> | 2014-09-18 15:57:06 +0900 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-09-29 19:35:57 +0200 |
| commit | ed0c83877f453b94a5e68bef62d6dbba1b97f0d2 (patch) | |
| tree | c0c3ba635505da345f65840cb2270556e7f13c19 /src/soc/intel/fsp_baytrail/baytrail/romstage.h | |
| parent | bdae9bedcdf5650abee089564c47ecbf2ba70f79 (diff) | |
| download | coreboot-ed0c83877f453b94a5e68bef62d6dbba1b97f0d2.tar.xz | |
intel/fsp_baytrail: Add S3 suspend/resume Support
This adds S3 Suspend / Resume support to Intel's Bay Trail FSP
It is based on the "src/soc/intel/baytrail/romstage/romstage.c"
implementation.
Change-Id: If0011068eb7290d1b764c5c4b12c17375fb69008
Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp>
Reviewed-on: http://review.coreboot.org/6937
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/fsp_baytrail/baytrail/romstage.h')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/baytrail/romstage.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_baytrail/baytrail/romstage.h b/src/soc/intel/fsp_baytrail/baytrail/romstage.h index 8feab8a3b4..1ceb4cf7cb 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/romstage.h +++ b/src/soc/intel/fsp_baytrail/baytrail/romstage.h @@ -33,6 +33,7 @@ void report_platform_info(void); #include <fsptypes.h> void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); +uint32_t chipset_prev_sleep_state(uint32_t clear); #define NUM_ROMSTAGE_TS 4 |