fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip

While similar to the Bay Trail-M/D code based on the MRC, there are
many differences as well:
- Obviously, uses the FSP instead of the MRC binaries.
- FSP does additional hardware setup, so coreboot doesn't need to.
- Different microcode & microcode loading method
- Uses the cache_as_ram.inc from the FSP Driver
- Various other changes in support of the FSP
Additional changes that don't have to to with the FSP vs MRC:
- Updated IRQ Routing
- Different FADT implementation.
This was validated with FSP:
BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
MD5: 9360cd915f0d3e4116bbc782233d7b91

Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5791
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 48 insertions, 0 deletions

diff --git a/src/soc/intel/fsp_baytrail/baytrail/smm.h b/src/soc/intel/fsp_baytrail/baytrail/smm.h
new file mode 100644
index 0000000000..0208c9f290
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/baytrail/smm.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BAYTRAIL_SMM_H_
+#define _BAYTRAIL_SMM_H_
+
+/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig
+ * is included after chipset code. This causes the chipset's Kconfig to be
+ * clobbered by the arch/x86/Kconfig if they have the same name. */
+static inline int smm_region_size(void)
+{
+#ifndef CONFIG_SMM_TSEG_SIZE
+#error CONFIG_SMM_TSEG_SIZE must be set.
+#endif
+
+	/* Make it 8MiB by default. */
+	if (CONFIG_SMM_TSEG_SIZE == 0)
+		return (8 << 20);
+	return CONFIG_SMM_TSEG_SIZE;
+}
+
+void *smm_region_start(void);
+
+#if !defined(__PRE_RAM__) && !defined(__SMM___)
+#include <stdint.h>
+void southcluster_smm_clear_state(void);
+void southcluster_smm_enable_smi(void);
+void southcluster_smm_save_gpio_route(uint32_t route);
+#endif
+
+#endif /* _BAYTRAIL_SMM_H_ */