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| author | Martin Roth <martin.roth@se-eng.com> | 2014-12-04 18:12:20 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-12-05 21:40:25 +0100 |
| commit | bb273162641f20efaa9e019ff9404f726439a431 (patch) | |
| tree | 774719c9161930c5c8494f466692c23ce7dec78f /src/soc/intel/fsp_baytrail/fsp | |
| parent | e10108a6691c804f4b917be9a25bc8af3d7cc6a1 (diff) | |
| download | coreboot-bb273162641f20efaa9e019ff9404f726439a431.tar.xz | |
fsp_baytrail: Update microcode for Gold 3 FSP release
New microcode for Bay Trail I B2/B3 and D0 parts was released in the
Gold 3 Bay Trail FSP release.
Change the microcode size to an area instead of the exact size of the
patches. This will hopefully reduce updates to the microcode size.
Change-Id: I58b4c57a4bb0e478ffd28bd74a5de6bb61540dfe
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7647
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/fsp')
0 files changed, 0 insertions, 0 deletions